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List: openjdk-hotspot-runtime-dev
Subject: Pls review 7142113: Add Ivy Bridge to the known Intel x86 cpu families (S)
From: paul.hohensee () oracle ! com (Paul Hohensee)
Date: 2012-02-17 19:11:02
Message-ID: 4F3EA646.2060804 () oracle ! com
[Download RAW message or body]
This isn't the complete check. supports_tscinv() is, vis.
static bool supports_tscinv_bit() {
return (_cpuFeatures & CPU_TSCINV) != 0;
}
static bool supports_tscinv() {
return supports_tscinv_bit() &&
( (is_amd() && !is_amd_Barcelona()) ||
is_intel_tsc_synched_at_init() );
}
There's a cpuid bit that is set when invariant tsc is supported. The
model check is there to restrict supports_tscinv() to platforms where
it's likely that the tsc is sync'ed across sockets.
Paul
On 2/16/12 8:55 PM, David Holmes wrote:
> On 17/02/2012 4:07 AM, Paul Hohensee wrote:
>> Did that. New webrev here
>>
>> http://cr.openjdk.java.net/~phh/7142113.03/
>>
>> This version lists all the model numbers >= nehalem known to me, and
>> allows
>> only the EP models in is_intel_tsc_synced_at_init().
>
> Given:
>
> 552 static bool is_intel_tsc_synched_at_init() {
> 553 if (is_intel_family_core()) {
> 554 uint32_t ext_model = extended_cpu_model();
> 555 if (ext_model == CPU_MODEL_NEHALEM_EP ||
> 556 ext_model == CPU_MODEL_WESTMERE_EP ||
> 557 ext_model == CPU_MODEL_SANDYBRIDGE_EP ||
> 558 ext_model == CPU_MODEL_IVYBRIDGE_EP) {
> 559 // <= 2-socket invariant tsc support. EX versions are
> usually used
> 560 // in > 2-socket systems and likely don't synchronize
> tscs at
> 561 // initialization.
> 562 // Code that uses tsc values must be prepared for them to
> arbitrarily
> 563 // jump forward or backward.
> 564 return true;
> 565 }
> 566 }
>
> does this mean there is no way to actually query the hardware to see
> if it has this capability? I hate seeing these code names in the
> sources - most of us don't need to track these names and would have no
> idea how they map to the processor (Xeon, i5, i7 etc) as described in
> the product documentation for a particular machine.
>
> David
> -----
>
>
>>
>> Thanks,
>>
>> Paul
>>
>> On 2/16/12 12:58 PM, Vladimir Kozlov wrote:
>>> Paul Hohensee wrote:
>>>> I should have said, I'd like to push this today so I'd like to make
>>>> checking
>>>> the socket count tbd. Is that ok?
>>>
>>> Yes, it is ok. It is for future changes.
>>>
>>> I think you should remove "Undocumented value" comment for 0x2d
>>> because it looks like Intel documents are out of day. It is newest
>>> version which is not reflected in documents yet.
>>>
>>> Vladimir
>>>
>>>>
>>>> Thanks,
>>>>
>>>> Paul
>>>>
>>>> On 2/16/12 12:23 PM, Paul Hohensee wrote:
>>>>> I'll change the comment to say we can figure it out but don't.
>>>>>
>>>>> Paul
>>>>>
>>>>> On 2/16/12 11:44 AM, Vladimir Kozlov wrote:
>>>>>> + // initialization. Hotspot doesn't currently figure out the number
>>>>>> + // of sockets,...
>>>>>>
>>>>>> Actually hotspot can do that. You can get it from CPUID processor
>>>>>> topology info or calculate it as:
>>>>>>
>>>>>> os::processor_count()/(cores_per_cpu() * threads_per_core())
>>>>>>
>>>>>> Vladimir
>>>>>>
>>>>>> On 2/16/12 8:12 AM, Vladimir Kozlov wrote:
>>>>>>> Wikipedia also points two models
>>>>>>>
>>>>>>> http://en.wikipedia.org/wiki/Intel_Sandy_Bridge_%28microarchitecture%29
>>>>>>>
>>>>>>>
>>>>>>>
>>>>>>> All Sandy Bridge processors with one, two, or four cores report
>>>>>>> the same CPUID model 0206A7h (0x2A) and are closely
>>>>>>> related... The later Sandy Bridge-E processors with up to six
>>>>>>> cores and no graphics are using CPUID 0206D6h (0x2D).
>>>>>>>
>>>>>>> Vladimir
>>>>>>>
>>>>>>> On 2/16/12 7:51 AM, Paul Hohensee wrote:
>>>>>>>> Would you point me at where you got the info, pls?
>>>>>>>>
>>>>>>>> Seems like both 42 and 45 are Sandy Bridge, just different
>>>>>>>> versions.
>>>>>>>>
>>>>>>>> Paul
>>>>>>>>
>>>>>>>> On 2/16/12 10:46 AM, Vladimir Kozlov wrote:
>>>>>>>>> Family 6, Model 26 (1Ah) = 45 nm Core i7 and Xeon (Nehalem)
>>>>>>>>> Family 6, Model 30 (1Eh) = 45 nm Core i5/i7 and Xeon (Nehalem)
>>>>>>>>> Family 6, Model 37 (25h) = 32 nm Core i3 (and mobile Core i5/i7)
>>>>>>>>> (Westmere)
>>>>>>>>> Family 6, Model 42 (2Ah) = 32 nm Core i5/i7 (Sandy Bridge)
>>>>>>>>> Family 6, Model 44 (2Ch) = 32 nm Core i7 and Westmere-EP
>>>>>>>>> Family 6, Model 45 (2Dh) = Sandy Bridge-EP
>>>>>>>>> Family 6, Model 46 (2Eh) = Nehalem-EX
>>>>>>>>> Family 6, Model 47 (2Fh) = Westmere-EX/E7
>>>>>>>>>
>>>>>>>>> But ask Intel first.
>>>>>>>>>
>>>>>>>>> Vladimir
>>>>>>>>>
>>>>>>>>> On 2/16/12 6:55 AM, Paul Hohensee wrote:
>>>>>>>>>> You're welcome.
>>>>>>>>>>
>>>>>>>>>> I found a Sandy Bridge machine in the Intel collab farm that
>>>>>>>>>> has a
>>>>>>>>>> model number of 45, so I'm going to keep both the documented
>>>>>>>>>> value of 42 and the apparently undocumented value of 45.
>>>>>>>>>>
>>>>>>>>>> New webrev here
>>>>>>>>>>
>>>>>>>>>> http://cr.openjdk.java.net/~phh/7142113.01/
>>>>>>>>>>
>>>>>>>>>> Absent objection, I'll push this version.
>>>>>>>>>>
>>>>>>>>>> Paul
>>>>>>>>>>
>>>>>>>>>> On 2/16/12 3:33 AM, Markus Gr?nlund wrote:
>>>>>>>>>>> Looks good Paul, thanks for doing this.
>>>>>>>>>>>
>>>>>>>>>>> I can tick off the IvyBridge CPUID on my list.
>>>>>>>>>>>
>>>>>>>>>>> Cheers
>>>>>>>>>>> Markus
>>>>>>>>>>>
>>>>>>>>>>>> -----Original Message-----
>>>>>>>>>>>> From: Paul Hohensee
>>>>>>>>>>>> Sent: den 16 februari 2012 03:44
>>>>>>>>>>>> To: Karen Kinnear
>>>>>>>>>>>> Cc: hotspot-runtime-dev at openjdk.java.net
>>>>>>>>>>>> Subject: Re: Pls review 7142113: Add Ivy Bridge to the known
>>>>>>>>>>>> Intel x86
>>>>>>>>>>>> cpu families (S)
>>>>>>>>>>>>
>>>>>>>>>>>> Thank you, Karen,
>>>>>>>>>>>>
>>>>>>>>>>>> Paul
>>>>>>>>>>>>
>>>>>>>>>>>> On 2/15/12 8:08 PM, Karen Kinnear wrote:
>>>>>>>>>>>>> Paul,
>>>>>>>>>>>>>
>>>>>>>>>>>>> Looks good - and thanks for fixing the SANDYBRIDGE id as
>>>>>>>>>>>>> well.
>>>>>>>>>>>>>
>>>>>>>>>>>>> thanks,
>>>>>>>>>>>>> Karen
>>>>>>>>>>>>>
>>>>>>>>>>>>> On Feb 15, 2012, at 4:53 PM, Paul Hohensee wrote:
>>>>>>>>>>>>>
>>>>>>>>>>>>>> Webrev here
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> http://cr.openjdk.java.net/~phh/7142113.00/
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Intel documentation (attached to the CR) says that the Ivy
>>>>>>>>>>>>>> Bridge
>>>>>>>>>>>> extended
>>>>>>>>>>>>>> model number is 0x3a.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> I changed the cpuExtendedModel values from decimal to hex,
>>>>>>>>>>>>>> since hex
>>>>>>>>>>>> is
>>>>>>>>>>>>>> what's used in the Intel documentation. I also changed
>>>>>>>>>>>> CPU_MODEL_SANDYBRIDGE_EP
>>>>>>>>>>>>>> from 0x2d == 45 to the correct 0x2a and added *_EX model
>>>>>>>>>>>>>> values for
>>>>>>>>>>>>>> later use: see comment in is_intel_tsc_synced_at_init().
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Tested on a Sandy Bridge machine via debugging
>>>>>>>>>>>>>> tty->print_cr(). I
>>>>>>>>>>>> don't
>>>>>>>>>>>>>> have access to an Ivy Bridge machine.
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Thanks,
>>>>>>>>>>>>>>
>>>>>>>>>>>>>> Paul
>>>>>>>>>>>>>>
>>>>>>>>>>>>>>
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