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List:       openjdk-hotspot-compiler-dev
Subject:    Re: pipeline class for sequence of instructions
From:       Edward Nevill <edward.nevill () gmail ! com>
Date:       2015-06-22 12:47:06
Message-ID: 1434977226.21282.14.camel () mint
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On Wed, 2015-06-17 at 19:34 +0000, Alexeev, Alexander wrote:


> Stages for arguments read/writes, decoder and execution unit are specified only \
> once. Is it then applied on every instructions that uses that pipeline class \
> arguments or for the whole ins_encode body?

AFAIUI

It is the whole ins_encode body. The pipeline scheduler does not go inside an AD \
instruct %{ ... %}

I would use the read parameters for the first instruction, and the write parameters \
for the last instruction. If a resource is used just list it as being used in the \
normal place you would expect such a resource to be used.

I think the pipeline scheduler is not really designed for multi instruction sequences \
so you have to just do the best you can to model the multi instruction sequence as a \
single fictitious instruction. 

Interestingly, in the example you chose below, I think it should be \
ins_pipe(ialu_reg_reg) rather than ins_pipe(ialu_reg) because countLeadingZerosL_bsr \
has both src and dst registers.

All the best,
Ed.

> // Integer ALU reg operation
> pipe_class ialu_reg(rRegI dst)
> %{
> single_instruction;
> dst    : S4(write);
> dst    : S3(read);
> DECODE : S0;        // any decoder
> ALU    : S3;        // any alu
> %}
> 
> 
> 
> instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
> predicate(!UseCountLeadingZerosInstruction);
> match(Set dst (CountLeadingZerosL src));
> effect(KILL cr);
> 
> format %{ "bsrq    $dst, $src\t# count leading zeros (long)\n\t"
> "jnz     skip\n\t"
> "movl    $dst, -1\n"
> "skip:\n\t"
> "negl    $dst\n\t"
> "addl    $dst, 63" %}
> ins_encode %{
> Register Rdst = $dst$$Register;
> Register Rsrc = $src$$Register;
> Label skip;
> __ bsrq(Rdst, Rsrc);
> __ jccb(Assembler::notZero, skip);
> __ movl(Rdst, -1);
> __ bind(skip);
> __ negl(Rdst);
> __ addl(Rdst, BitsPerLong - 1);
> %}
> ins_pipe(ialu_reg);
> %}


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