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List:       netbsd-port-sparc
Subject:    SX, S24 and so on
From:       Michael <macallan () NetBSD ! org>
Date:       2008-12-30 5:07:06
Message-ID: 1FD952C6-15C4-4F5D-AAFE-342643FE5F08 () netbsd ! org
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Hello,

after some more poking around regarding the /SUNW,sx rendering engine  
found in the SS20's memory controller it looks like figuring out how  
the thing works is more complicated than expected. Apparently the  
thing is actually some sort of CPU and the registers are only for  
starting and stopping it, to configure which memory ranges it can see  
and some communication ( like dealing with errors and sending it  
commands ). There's an IEEE paper describing the SX ( 'Pixel  
processing in a memory controller', http://ieeexplore.ieee.org/iel1/38/8361/00364964.pdf 
  ) but I have no idea to which level of detail - probably not enough  
to write a driver - and it's not accessible without forking over some  
money. Buying the cat in a bag.

In other news, I have an SS5 now, so writing a TCX/S24 driver is only  
a matter of getting my hands on such a board. I'm pretty sure I have  
enough information to write accelerated drivers for both X and the  
NetBSD console.

have fun
Michael

-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.7 (Darwin)

iQEVAwUBSVmsespnzkX8Yg2nAQKcZgf9HOcLBNzohOj5FSYh7qOUVYXpDX6yROm7
ZCoMI95890rwHMz+WqTU4KOKc7Rd9k/s4Dqc1h5dRcDzabCJIA4YzF2HdLWOUrnP
jX7NIrsi8ac/K9sd2FR56sGssnKCu3U+Nrys6Y7wnBN8R3X2eYRLQbxk7xzWB50s
8zt6/2kfSf0kQUGSdJkWnYJc2xE6i1eEIU5IqCcqk6prRugQamog49I/HBgUqPB7
BRpL9xIH2Tz2NzAewWtTgLzCTA3ONx7DnclGrmq0d4AtF4NrJETFWN4+XCH6AoIC
TFOLw+lBHbxxaBa9hBMKJpGM5aypvMsujab+oqJHAbHPxWoDb3PBDw==
=dPle
-----END PGP SIGNATURE-----

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