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List:       netbsd-port-arm
Subject:    BeagleBone (AM335x) gpio
From:       Paul ONeill <hponeill633 () dendra ! net>
Date:       2014-05-05 6:09:25
Message-ID: 1399270165.6027.0 () Starbug ! local
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Updated Patches to get gpio working on the beaglebone.

What works: Basic gpio using the gpioctl command.
What does not yet work: gpio pin interrupts.


Index: BEAGLEBONE
===================================================================
RCS file: /cvsroot/src/sys/arch/evbarm/conf/BEAGLEBONE,v
retrieving revision 1.20
diff -u -r1.20 BEAGLEBONE
--- BEAGLEBONE	16 Aug 2013 02:21:53 -0000	1.20
+++ BEAGLEBONE	5 May 2014 05:41:00 -0000
@@ -207,14 +207,31 @@
  #options SDMMC_DEBUG
  #options SDHC_DEBUG

+
  # General-purpose I/O pins
-# XXX These are the GPIO v2 in the AM335x, not v1 as in the OMAP35xx.
-#omapgpio0	at obio0 addr 0x44e07000 size 0x1000 intrbase 128 intr  
29
-#omapgpio1	at obio0 addr 0x4804c000 size 0x1000 intrbase 160 intr  
30
-#omapgpio2	at obio0 addr 0x481ac000 size 0x1000 intrbase 192 intr  
32
-#omapgpio3	at obio0 addr 0x481ae000 size 0x1000 intrbase 224 intr  
32
+#
+#omapgpio0 at obio0 addr 0x44e07000 size 0x1000 intrbase 128 intr 96
+#omapgpio1 at obio0 addr 0x4804c000 size 0x1000 intrbase 160 intr 98
+#omapgpio2 at obio0 addr 0x481ac000 size 0x1000 intrbase 192 intr 32
+#omapgpio3 at obio0 addr 0x481ae000 size 0x1000 intrbase 224 intr 62
+
+# GPIO interrupts are not yet working
+# Disable them by setting the interrupt base to -1
+#
+omapgpio0 at obio0 addr 0x44e07000 size 0x1000 intrbase -1 intr 96
+omapgpio1 at obio0 addr 0x4804c000 size 0x1000 intrbase -1 intr 98
+omapgpio2 at obio0 addr 0x481ac000 size 0x1000 intrbase -1 intr 32
+omapgpio3 at obio0 addr 0x481ae000 size 0x1000 intrbase -1 intr 62
+
+# Nail down the ports to specific device files
+#
+gpio0          at omapgpio0
+gpio1          at omapgpio1
+gpio2          at omapgpio2
+gpio3          at omapgpio3
+
+#gpio*         at omapgpio?

-#gpio*		at omapgpio?

  # I2C Controller
  tiiic0		at obio0 addr 0x44e0b000 size 0x1000 intr 70



Index: omap2_gpio.c
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/omap/omap2_gpio.c,v
retrieving revision 1.16
diff -u -r1.16 omap2_gpio.c
--- omap2_gpio.c	15 Jun 2013 21:59:37 -0000	1.16
+++ omap2_gpio.c	5 May 2014 05:46:33 -0000
@@ -171,7 +171,7 @@
  	 * Make sure the irq isn't enabled and not asserting.
  	 */
  	gpio->gpio_enable_mask &= ~irq_mask;
-	GPIO_WRITE(gpio, GPIO_IRQENABLE1, gpio->gpio_enable_mask);
+	GPIO_WRITE(gpio, GPIO_CLEARIRQENABLE1, irq_mask);
  	GPIO_WRITE(gpio, GPIO_IRQSTATUS1, irq_mask);

  	/*


Index: omap2_reg.h
===================================================================
RCS file: /cvsroot/src/sys/arch/arm/omap/omap2_reg.h,v
retrieving revision 1.27
diff -u -r1.27 omap2_reg.h
--- omap2_reg.h	4 Apr 2014 21:33:19 -0000	1.27
+++ omap2_reg.h	5 May 2014 05:46:03 -0000
@@ -767,6 +767,46 @@
  #define	GPIO5_BASE_TI_DM37XX		0x49056000
  #define	GPIO6_BASE_TI_DM37XX		0x49058000

+#ifdef TI_AM335X
+#define GPIO_REVISION			0x000
+#define GPIO_SYSCONFIG			0x010
+#define GPIO_EOI				0x020
+#define GPIO_IRQSTATUS_RAW_0	0x024
+#define GPIO_IRQSTATUS_RAW_1	0x028
+#define GPIO_IRQSTATUS_0		0x02c
+#define GPIO_IRQSTATUS_1		0x030
+#define GPIO_IRQSTATUS_SET_0	0x034
+#define GPIO_IRQSTATUS_SET_1	0x038
+#define GPIO_IRQSTATUS_CLR_0	0x03c
+#define GPIO_IRQSTATUS_CLR_1	0x040
+#define GPIO_IRQWAKEN_0			0x044
+#define GPIO_IRQWAKEN_1			0x048
+#define GPIO_SYSSTATUS			0x114
+#define GPIO_CTRL				0x130
+#define GPIO_OE					0x134
+#define GPIO_DATAIN				0x138
+#define GPIO_DATAOUT			0x13c
+#define GPIO_LEVELDETECT0		0x140
+#define GPIO_LEVELDETECT1		0x144
+#define GPIO_RISINGDETECT		0x148
+#define GPIO_FALLINGDETECT		0x14c
+#define GPIO_DEBOUNCENABLE		0x150
+#define GPIO_DEBOUNINGTIME		0x154
+#define GPIO_CLEARDATAOUT		0x190
+#define GPIO_SETDATAOUT			0x194
+
+/*
+ * Translate some register names for generic omap gpio driver
+ */
+
+#define GPIO_IRQSTATUS1			GPIO_IRQSTATUS_0
+#define GPIO_IRQSTATUS2			GPIO_IRQSTATUS_1
+
+#define GPIO_SETIRQENABLE1		GPIO_IRQSTATUS_SET_0
+#define GPIO_SETIRQENABLE2		GPIO_IRQSTATUS_SET_1
+#define GPIO_CLEARIRQENABLE1	GPIO_IRQSTATUS_CLR_0
+#define GPIO_CLEARIRQENABLE2	GPIO_IRQSTATUS_CLR_1
+#else
  #define	GPIO_IRQSTATUS1			0x018
  #define	GPIO_IRQENABLE1			0x01c
  #define	GPIO_WAKEUPENABLE		0x020
@@ -790,6 +830,7 @@
  #define	GPIO_SETWKUENA			0x084
  #define	GPIO_CLEARDATAOUT		0x090
  #define	GPIO_SETDATAOUT			0x094
+#endif

  /*
   * I2C


=
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