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List: llvm-commits
Subject: [PATCH] D37317: [X86] Don't pull carry through X86ISD::ADD carryin, -1 if we can't guranteed we're r
From: Phabricator via Phabricator via llvm-commits <llvm-commits () lists ! llvm ! org>
Date: 2017-08-31 21:40:49
Message-ID: db7f9080969ef58146f1386e378a15ce () localhost ! localdomain
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This revision was automatically updated to reflect the committed changes.
Closed by commit rL312285: [X86] Don't pull carry through X86ISD::ADD carryin, -1 if \
we can't guranteed… (authored by ctopper).
Changed prior to commit:
https://reviews.llvm.org/D37317?vs=113449&id=113479#toc
Repository:
rL LLVM
https://reviews.llvm.org/D37317
Files:
llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
["D37317.113479.patch" (text/x-patch)]
Index: llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
===================================================================
--- llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
+++ llvm/trunk/lib/Target/X86/X86ISelLowering.cpp
@@ -30939,11 +30939,40 @@
return true;
}
+// When legalizing carry, we create carries via add X, -1
+// If that comes from an actual carry, via setcc, we use the
+// carry directly.
+static SDValue combineCarryThroughADD(SDValue EFLAGS) {
+ if (EFLAGS.getOpcode() == X86ISD::ADD) {
+ if (isAllOnesConstant(EFLAGS.getOperand(1))) {
+ SDValue Carry = EFLAGS.getOperand(0);
+ while (Carry.getOpcode() == ISD::TRUNCATE ||
+ Carry.getOpcode() == ISD::ZERO_EXTEND ||
+ Carry.getOpcode() == ISD::SIGN_EXTEND ||
+ Carry.getOpcode() == ISD::ANY_EXTEND ||
+ (Carry.getOpcode() == ISD::AND &&
+ isOneConstant(Carry.getOperand(1))))
+ Carry = Carry.getOperand(0);
+ if (Carry.getOpcode() == X86ISD::SETCC ||
+ Carry.getOpcode() == X86ISD::SETCC_CARRY) {
+ if (Carry.getConstantOperandVal(0) == X86::COND_B)
+ return Carry.getOperand(1);
+ }
+ }
+ }
+
+ return SDValue();
+}
+
/// Optimize an EFLAGS definition used according to the condition code \p CC
/// into a simpler EFLAGS value, potentially returning a new \p CC and replacing
/// uses of chain values.
static SDValue combineSetCCEFLAGS(SDValue EFLAGS, X86::CondCode &CC,
SelectionDAG &DAG) {
+ if (CC == X86::COND_B)
+ if (SDValue Flags = combineCarryThroughADD(EFLAGS))
+ return Flags;
+
if (SDValue R = checkBoolTestSetCCCombine(EFLAGS, CC))
return R;
return combineSetCCAtomicArith(EFLAGS, CC, DAG);
@@ -34987,27 +35016,13 @@
return SDValue();
}
-// Optimize RES, EFLAGS = X86ISD::ADD LHS, RHS
-static SDValue combineX86ADD(SDNode *N, SelectionDAG &DAG,
- X86TargetLowering::DAGCombinerInfo &DCI) {
- // When legalizing carry, we create carries via add X, -1
- // If that comes from an actual carry, via setcc, we use the
- // carry directly.
- if (isAllOnesConstant(N->getOperand(1)) && N->hasAnyUseOfValue(1)) {
- SDValue Carry = N->getOperand(0);
- while (Carry.getOpcode() == ISD::TRUNCATE ||
- Carry.getOpcode() == ISD::ZERO_EXTEND ||
- Carry.getOpcode() == ISD::SIGN_EXTEND ||
- Carry.getOpcode() == ISD::ANY_EXTEND ||
- (Carry.getOpcode() == ISD::AND &&
- isOneConstant(Carry.getOperand(1))))
- Carry = Carry.getOperand(0);
-
- if (Carry.getOpcode() == X86ISD::SETCC ||
- Carry.getOpcode() == X86ISD::SETCC_CARRY) {
- if (Carry.getConstantOperandVal(0) == X86::COND_B)
- return DCI.CombineTo(N, SDValue(N, 0), Carry.getOperand(1));
- }
+static SDValue combineSBB(SDNode *N, SelectionDAG &DAG) {
+ if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
+ MVT VT = N->getSimpleValueType(0);
+ SDVTList VTs = DAG.getVTList(VT, MVT::i32);
+ return DAG.getNode(X86ISD::SBB, SDLoc(N), VTs,
+ N->getOperand(0), N->getOperand(1),
+ Flags);
}
return SDValue();
@@ -35036,6 +35051,14 @@
return DCI.CombineTo(N, Res1, CarryOut);
}
+ if (SDValue Flags = combineCarryThroughADD(N->getOperand(2))) {
+ MVT VT = N->getSimpleValueType(0);
+ SDVTList VTs = DAG.getVTList(VT, MVT::i32);
+ return DAG.getNode(X86ISD::ADC, SDLoc(N), VTs,
+ N->getOperand(0), N->getOperand(1),
+ Flags);
+ }
+
return SDValue();
}
@@ -35721,7 +35744,7 @@
case X86ISD::CMOV: return combineCMov(N, DAG, DCI, Subtarget);
case ISD::ADD: return combineAdd(N, DAG, Subtarget);
case ISD::SUB: return combineSub(N, DAG, Subtarget);
- case X86ISD::ADD: return combineX86ADD(N, DAG, DCI);
+ case X86ISD::SBB: return combineSBB(N, DAG);
case X86ISD::ADC: return combineADC(N, DAG, DCI);
case ISD::MUL: return combineMul(N, DAG, DCI, Subtarget);
case ISD::SHL:
[Attachment #4 (text/plain)]
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