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List:       llvm-commits
Subject:    [llvm-commits] CVS: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
From:       "Andrew Lenharth" <alenhar2 () cs ! uiuc ! edu>
Date:       2005-06-27 21:03:07
Message-ID: 200506272103.QAA31585 () zion ! cs ! uiuc ! edu
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Changes in directory llvm/lib/Target/Alpha:

AlphaISelPattern.cpp updated: 1.133 -> 1.134
AlphaInstrInfo.td updated: 1.46 -> 1.47
---
Log message:

generate address of constant pool entries

---
Diffs of the changes:  (+10 -5)

 AlphaISelPattern.cpp |   14 +++++++++-----
 AlphaInstrInfo.td    |    1 +
 2 files changed, 10 insertions(+), 5 deletions(-)


Index: llvm/lib/Target/Alpha/AlphaISelPattern.cpp
diff -u llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.133 \
                llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.134
--- llvm/lib/Target/Alpha/AlphaISelPattern.cpp:1.133	Mon Jun 27 12:39:17 2005
+++ llvm/lib/Target/Alpha/AlphaISelPattern.cpp	Mon Jun 27 16:02:56 2005
@@ -1520,11 +1520,15 @@
     BuildMI(BB, Alpha::BIS, 2, Result).addReg(Alpha::R30).addReg(Alpha::R30);
     return Result;
 
-//   case ISD::ConstantPool:
-//     Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
-//     AlphaLowering.restoreGP(BB);
-//     BuildMI(BB, Alpha::LDQ_SYM, 1, Result).addConstantPoolIndex(Tmp1);
-//     return Result;
+  case ISD::ConstantPool:
+    Tmp1 = cast<ConstantPoolSDNode>(N)->getIndex();
+    AlphaLowering.restoreGP(BB);
+    Tmp2 = MakeReg(MVT::i64);
+    BuildMI(BB, Alpha::LDAHr, 2, Tmp2).addConstantPoolIndex(Tmp1)
+      .addReg(Alpha::R29);
+    BuildMI(BB, Alpha::LDAr, 2, Result).addConstantPoolIndex(Tmp1)
+      .addReg(Tmp2);
+    return Result;
 
   case ISD::FrameIndex:
     BuildMI(BB, Alpha::LDA, 2, Result)


Index: llvm/lib/Target/Alpha/AlphaInstrInfo.td
diff -u llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.46 \
                llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.47
--- llvm/lib/Target/Alpha/AlphaInstrInfo.td:1.46	Mon Jun 27 12:15:36 2005
+++ llvm/lib/Target/Alpha/AlphaInstrInfo.td	Mon Jun 27 16:02:56 2005
@@ -369,6 +369,7 @@
 def LDTr : MForm<0x23, (ops FPRC:$RA, s16imm:$DISP, GPRC:$RB), "ldt $RA,$DISP($RB) \
!gprellow">; //Load T_floating  
 //Load address, rellocated form
+def LDAr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, GPRC:$RB), "lda $RA,$DISP($RB) \
!gprellow">;  //Load address  def LDAHr : MForm<0x08, (ops GPRC:$RA, s16imm:$DISP, \
GPRC:$RB), "ldah $RA,$DISP($RB) !gprelhigh">;  //Load address high  
 


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