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List: linuxbios
Subject: [coreboot] Re: Coffee Lake Reset S5 Problem
From: Maximilian Brune <maximilian.brune () 9elements ! com>
Date: 2023-03-29 20:46:45
Message-ID: CAGrcQaRavEEC=xAA8P9x32MSuS6=1Hacf4-h5qBL+GBt40t+yw () mail ! gmail ! com
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Not really familiar with the PIC32, but do you have some kind of logs for
it? The PIC32 should get the usual power sequence signals from the PCH and
acknowledge them before the host gets back to the reset vector. I had a
similar case in the past where the PCH repeated sending the power
sequencing signals but the EC (in your case PIC32) failed to acknowledge
them (which resulted the Host to get stuck). I know you said that you
tested the same setup with slimbootloader, but that's the best I can
currently come up with.
Am Mi., 29. März 2023 um 07:49 Uhr schrieb <cagataybag@yahoo.com>:
>
> Our design is similar to RVP except that we have PIC32 instead of EC and
> we have RAM soldered on board. So power sequences and other settings are
> controlled by PIC32. The only changes I did are putting appropriate spd
> binary and changing spd read type. I added log as attachment. I am building
> full spi image with Intel Fit Tool.
>
> We tested our board with this configuration with another open source bios,
> Slimbootloader and were able to boot OS.
>
> On Salı, Mart 28, 2023, 8:41 ÖS, Maximilian Brune <
> maximilian.brune@9elements.com> wrote:
>
> What do you mean by "microcontroller"? ME? EC?
> Does it work on the reference BIOS?
> Which EC Firmware are you using?
>
> Am Di., 28. März 2023 um 16:00 Uhr schrieb Paul Menzel <
> pmenzel@molgen.mpg.de>:
>
>
> Dear Cagatay,
>
>
> Welcome to coreboot!
>
> Am 28.03.23 um 15:49 schrieb cagatay bagci via coreboot:
> > We have a custom CFL board that resembles CFL RVP-11. I compiled the
> > code and flashed it and it started booting without problem. However
> > after global reset, it stucks at S5 and S5 signal asserts low.
> > Because of that, microcontroller does not power up the system. What
> > might be the problem?
> >
> > Log is ending here:
> >
> > [INFO ] Done allocating resources.
> > [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 75 ms
> > [DEBUG] GLOBAL RESET!
> > [INFO ] global_reset() called!
> > [DEBUG] HECI: Global Reset(Type:1) Command
>
> Please attach the full log – also formatted to not have the console
> control sequences in it. Just to be sure, you are running unmodified
> code? If not, please point to the changes you did.
>
>
> Kind regards,
>
> Paul
> _______________________________________________
> coreboot mailing list -- coreboot@coreboot.org
> To unsubscribe send an email to coreboot-leave@coreboot.org
>
> _______________________________________________
> coreboot mailing list -- coreboot@coreboot.org
> To unsubscribe send an email to coreboot-leave@coreboot.org
>
>
[Attachment #5 (text/html)]
<div dir="ltr">Not really familiar with the PIC32, but do you have some kind of logs \
for it? The PIC32 should get the usual power sequence signals from the PCH and \
acknowledge them before the host gets back to the reset vector. I had a similar case \
in the past where the PCH repeated sending the power sequencing signals but the EC \
(in your case PIC32) failed to acknowledge them (which resulted the Host to get \
stuck). I know you said that you tested the same setup with slimbootloader, but \
that's the best I can currently come up with.<br></div><br><div \
class="gmail_quote"><div dir="ltr" class="gmail_attr">Am Mi., 29. März 2023 um 07:49 \
Uhr schrieb <<a href="mailto:cagataybag@yahoo.com">cagataybag@yahoo.com</a>>:<br></div><blockquote \
class="gmail_quote" style="margin:0px 0px 0px 0.8ex;border-left:1px solid \
rgb(204,204,204);padding-left:1ex"><div>
<br>Our design is similar to RVP except that we have PIC32 instead of EC and we have \
RAM soldered on board. So power sequences and other settings are controlled by PIC32. \
The only changes I did are putting appropriate spd binary and changing spd read \
type. I added log as attachment. I am building full spi image with Intel Fit Tool. \
<div><br></div><div>We tested our board with this configuration with another open \
source bios, Slimbootloader and were able to boot OS.<span \
id="m_-8560180186652719154yahoo-rte-cursor-span"></span><br><br><p \
style="font-size:15px;color:rgb(113,95,250);padding-top:15px;margin-top:0px">On \
Salı, Mart 28, 2023, 8:41 ÖS, Maximilian Brune <<a \
href="mailto:maximilian.brune@9elements.com" \
target="_blank">maximilian.brune@9elements.com</a>> wrote:</p><blockquote><div \
id="m_-8560180186652719154yiv4753088506"><div><div dir="ltr"><div>What do you mean by \
"microcontroller"? ME? EC?</div><div>Does it work on the reference \
BIOS?</div><div>Which EC Firmware are you using?<br clear="none"></div></div><br \
clear="none"><div><div dir="ltr">Am Di., 28. März 2023 um 16:00 Uhr schrieb Paul \
Menzel <<a rel="nofollow noopener noreferrer" shape="rect" \
href="mailto:pmenzel@molgen.mpg.de" target="_blank">pmenzel@molgen.mpg.de</a>>:<br \
clear="none"></div><div id="m_-8560180186652719154yiv4753088506yqt68794"><blockquote \
style="margin:0px 0px 0px 0.8ex;border-left:1px solid \
rgb(204,204,204);padding-left:1ex"><br clear="none"> Dear Cagatay,<br clear="none">
<br clear="none">
<br clear="none">
Welcome to coreboot!<br clear="none">
<br clear="none">
Am 28.03.23 um 15:49 schrieb cagatay bagci via coreboot:<br clear="none">
> We have a custom CFL board that resembles CFL RVP-11. I compiled the<br \
clear="none"> > code and flashed it and it started booting without problem. \
However<br clear="none"> > after global reset, it stucks at S5 and S5 signal \
asserts low.<br clear="none"> > Because of that, microcontroller does not power up \
the system. What<br clear="none"> > might be the problem?<br clear="none">
> <br clear="none">
> Log is ending here:<br clear="none">
> <br clear="none">
> [INFO ] Done allocating resources.<br clear="none">
> [DEBUG] BS: BS_DEV_RESOURCES run times (exec / console): 3 / 75 ms<br \
clear="none"> > [DEBUG] GLOBAL RESET!<br clear="none">
> [INFO ] global_reset() called!<br clear="none">
> [DEBUG] HECI: Global Reset(Type:1) Command<br clear="none">
<br clear="none">
Please attach the full log – also formatted to not have the console <br \
clear="none"> control sequences in it. Just to be sure, you are running unmodified \
<br clear="none"> code? If not, please point to the changes you did.<br clear="none">
<br clear="none">
<br clear="none">
Kind regards,<br clear="none">
<br clear="none">
Paul<br clear="none">
_______________________________________________<br clear="none">
coreboot mailing list -- <a rel="nofollow noopener noreferrer" shape="rect" \
href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br \
clear="none"> To unsubscribe send an email to <a rel="nofollow noopener noreferrer" \
shape="rect" href="mailto:coreboot-leave@coreboot.org" \
target="_blank">coreboot-leave@coreboot.org</a><br clear="none"> \
</blockquote></div></div> </div></div><div \
id="m_-8560180186652719154yqt87996">_______________________________________________<br \
clear="none">coreboot mailing list -- <a shape="rect" \
href="mailto:coreboot@coreboot.org" target="_blank">coreboot@coreboot.org</a><br \
clear="none">To unsubscribe send an email to <a shape="rect" \
href="mailto:coreboot-leave@coreboot.org" \
target="_blank">coreboot-leave@coreboot.org</a><br \
clear="none"></div><blockquote></blockquote></blockquote> </div>
</div></blockquote></div>
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