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List:       linuxbios
Subject:    [coreboot] =?utf-8?q?Re=3A_Specifying_image_size_=28was=3A_=E2=80=A6_and_cpu-flash_addresses=2E=29?=
From:       Paul Menzel <pmenzel () molgen ! mpg ! de>
Date:       2022-08-07 6:55:41
Message-ID: b6d757f4-4a7f-36e2-8480-61b8921953f7 () molgen ! mpg ! de
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Dear Pedro,


Am 06.08.22 um 18:45 schrieb Pedro Erencia:

> I was going to try coreboot on an ASROCK FM2A88X Extreme4+ (
> https://www.asrock.com/mb/AMD/FM2A88X%20Extreme4+/) with the configuration
> of the supported ASUS A88XM-E (
> https://doc.coreboot.org/mainboard/asus/a88xm-e.html) which has the same
> chipset (A88X Bolton).

Welcome to coreboot. There is a very small chance, that using an image 
from another board might damage the board due to GPIOs being 
misconfigured, and a short-circuit is programmed.

> The fact is that, at this moment, I only have a 16 MiB flash, while the
> image is 8 MiB. As the chipset claims that it
> "Supports a maximum SPI ROM size of 16MB" I think there should be no
> problem, but I wonder how I have to burn the image. That led me to the
> question of how the translation between CPU and flash addresses are done.
> For supporting various ROM sizes, I guess the controller should somehow
> know the size of the ROM, but I don't see anywhere where that could be
> specified.

In `make menuconfig` in the section *Mainboard* adapt

     ROM chip size (8192 KB (8 MB))  --->

to 16 MB. But it might be useful to also adapt the size for the CBFS 
filesystem in ROM. (It's automatically adapted if you delete `.config` 
beforehand.)

In the past, taking the 8 MB file, and concatenating it twice to a 16 MB 
image also worked.

[…]


Kind regards,

Paul
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