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List: linuxbios
Subject: [coreboot] Re: coreboot image forIntel Harcuvar CRB
From: Tirumalesh <tirumalesh () chalamarla ! com>
Date: 2021-02-07 9:43:09
Message-ID: C-4BJsnd2Mgbza58EIpMI5lb6o0anmZ2vFsjgnJwjZYyf0bHRvZMQuujHIf8s5YYnVG1QGrfdGcB0rVUfFMB97AtPZSPLCbEJ8tmEHuakaw= () chalamarla ! com
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Hi Mariusz,
Thank you!, that helped.
Thanks,
Tirumalesh.
------- Original Message -------
On Friday, February 5, 2021 3:01 PM, Szafranski, MariuszX \
<mariuszx.szafranski@intel.com> wrote:
> Hi Tirumalesh,
>
> Please verify if FSP is correctly integrated. Especially if FSP-T part is enabled \
> and used for setting up CAR.
> config mainboard section:
>
> vendor->Intel,
>
> model->Harcuvar,
>
> romsize ->16M, (insert your actual SPI flash size)
>
> cbfs size 8M (0x800000) (or adjust for your needs)
>
> config chipset:
>
> check Enable High-speed UART debug port selected by UART_FOR_CONSOLE (enable for \
> non legacy UART mode, disable for legacy)
> cache as ram implementation -> Use FSP CAR
>
> UART mode – leave at default non legacy mode (or enable if needed – adjust \
> other settings for legacy mode)
> Verify if generate from tree is selected for microcode (Include CPU microcode in \
> CBFS (Generate from tree))
> config generic drivers:
>
> UART's PCI bus, device, function address - 0x8000d000
>
> Verify if "serial port" on superior is unchecked (need to be when using UART in \
> legacy mode)
> config console:
>
> verify if two first options (bootblock console and postcar console) are enabled
>
> As I remember there are two serial port connectors – check if you are using \
> correct one (try both)
> BR,
>
> Mariusz
>
> From: Tirumalesh <tirumalesh@chalamarla.com>
> Sent: Friday, February 5, 2021 8:54 AM
> To: Javier Galindo <javiergalindo@sysproconsulting.com>; coreboot@coreboot.org
> Subject: [coreboot] Re: coreboot image forIntel Harcuvar CRB
>
> It seems the FSP binaries are auto included, and the configs seems to be of no \
> effect.
> Is it not right?
>
> If so I will try to add binaries and microcode header file.
>
> Thanks,
>
> Tirumalesh
>
> On Fri, Feb 5, 2021 at 11:22 AM, Javier Galindo \
> <javiergalindo@sysproconsulting.com> wrote:
> > Did you set the following in your config file --> CONFIG_LEGACY_UART_MODE=y
> >
> > Also have you setup all the proper fsp/ucode binaries that are commented out in \
> > the config file (just did a quick review):
> > #Sample settings for Denverton-NS FSP.
> > #CONFIG_ADD_FSP_BINARIES=y
> > #CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"
> > #CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"
> > #CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"
> > #CONFIG_FSP_CAR=y
> >
> > #Sample settings for microcode definitions.
> > #CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"
> > #CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y
> >
> > Unfortunately all my harcuvar work has also been on a fairly old tree of \
> > coreboot.
> > I'll give it a try on my Harcuvar if you don't make any progress, but it won't be \
> > until the weekend. _______________________________________________
> > coreboot mailing list -- coreboot@coreboot.org
> > To unsubscribe send an email to coreboot-leave@coreboot.org
>
> --------------------------------------------------------------
> Intel Research and Development Ireland Limited
> Registered in Ireland
> Registered Office: Collinstown Industrial Park, Leixlip, County Kildare
> Registered Number: 308263
>
> This e-mail and any attachments may contain confidential material for the sole use \
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<div><br></div><div>Hi <span style="background-color:rgb(255, 255, 255)"><span \
style="color:rgb(85, 85, 85)"><span style="font-family:Arial, "Helvetica \
Neue", Helvetica, sans-serif"><span \
style="font-size:14px">Mariusz,</span></span></span></span><br></div><div><br></div><div><span \
style="background-color:rgb(255, 255, 255)"><span style="color:rgb(85, 85, 85)"><span \
style="font-family:Arial, "Helvetica Neue", Helvetica, sans-serif"><span \
style="font-size:14px">Thank you!, that \
helped.</span></span></span></span><br></div><div><br></div><div>Thanks,<br></div><div>Tirumalesh.</div><div><br></div><div>------- \
Original Message -------<br></div><div> On Friday, February 5, 2021 3:01 PM, \
Szafranski, MariuszX <mariuszx.szafranski@intel.com> wrote:<br></div><div> \
<br></div><blockquote class="protonmail_quote" type="cite"><div><p><span lang="EN-US" \
style="mso-fareast-language:EN-US">Hi Tirumalesh,</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> </span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US">Please verify if FSP is correctly integrated. \
Especially if FSP-T part is enabled and used for setting up \
CAR.</span><br></p><p><span lang="EN-US" style="mso-fareast-language:EN-US">config \
mainboard section:</span><br></p><p style="text-indent:35.4pt"><span lang="EN-US" \
style="mso-fareast-language:EN-US">vendor->Intel,</span><br></p><p \
style="text-indent:35.4pt"><span lang="EN-US" \
style="mso-fareast-language:EN-US">model->Harcuvar,</span><br></p><p \
style="text-indent:35.4pt"><span lang="EN-US" \
style="mso-fareast-language:EN-US">romsize ->16M, (insert your actual SPI flash \
size)</span><br></p><p style="text-indent:35.4pt"><span lang="EN-US" \
style="mso-fareast-language:EN-US">cbfs size 8M (0x800000) (or adjust for your \
needs)</span><br></p><p><span lang="EN-US" style="mso-fareast-language:EN-US">config \
chipset:</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> \
check </span><span lang="EN-US"> </span><span lang="EN-US" \
style="mso-fareast-language:EN-US">Enable High-speed UART debug port selected by \
UART_FOR_CONSOLE (enable for non legacy UART mode, disable for \
legacy)</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> \
cache as ram implementation -> Use FSP CAR</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> \
UART mode – leave at default non legacy mode (or enable if needed – adjust other \
settings for legacy mode)</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> \
Verify if generate from tree is selected for microcode (Include CPU microcode in CBFS \
(Generate from tree))</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US">config generic drivers:</span><br></p><p><span \
lang="EN-US" style="mso-fareast-language:EN-US"> \
UART's PCI bus, device, function address - 0x8000d000</span><br></p><p><span \
lang="EN-US" style="mso-fareast-language:EN-US"> \
Verify if "serial port" on superior is unchecked (need to be when using UART in \
legacy mode)</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US">config console:</span><br></p><p><span \
lang="EN-US" style="mso-fareast-language:EN-US"> \
verify if two first options (bootblock console and postcar console) are \
enabled</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> </span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US">As I remember there are two serial port connectors \
– check if you are using correct one (try both)</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> </span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US">BR,</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US">Mariusz</span><br></p><p><span lang="EN-US" \
style="mso-fareast-language:EN-US"> </span><br></p><div \
style="border:none;border-top:solid #E1E1E1 1.0pt;padding:3.0pt 0in 0in \
0in"><p><b><span lang="EN-US">From:</span></b><span lang="EN-US"> Tirumalesh \
<tirumalesh@chalamarla.com> <br> <b>Sent:</b> Friday, February 5, 2021 8:54 \
AM<br> <b>To:</b> Javier Galindo <javiergalindo@sysproconsulting.com>; \
coreboot@coreboot.org<br> <b>Subject:</b> [coreboot] Re: coreboot image forIntel \
Harcuvar CRB</span></p></div><p> <br></p><div><p>It seems the FSP binaries are \
auto included, and the configs seems to be of no effect.<br></p></div><div><p>Is it \
not right?<br></p></div><div><p> <br></p></div><div><p>If so I will try to add \
binaries and microcode header \
file.<br></p></div><div><p> <br></p></div><div><p>Thanks,<br></p></div><div><p>Ti \
rumalesh <br></p></div><div><p> <br></p></div><div><p> <br></p></div><p>On \
Fri, Feb 5, 2021 at 11:22 AM, Javier Galindo <<a \
href="mailto:javiergalindo@sysproconsulting.com">javiergalindo@sysproconsulting.com</a>> \
wrote:<br></p><blockquote \
style="margin-top:5.0pt;margin-bottom:5.0pt"><p></p><div>Did you set the following in \
your config file --> CONFIG_LEGACY_UART_MODE=y<br></div><div> <br></div><div> Also \
have you setup all the proper fsp/ucode binaries that are commented out in the config \
file (just did a quick review):<br></div><div> <br></div><div> #Sample settings for \
Denverton-NS FSP.<br></div><div> #CONFIG_ADD_FSP_BINARIES=y<br></div><div> \
#CONFIG_FSP_M_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_M.fd"<br></div><div> \
#CONFIG_FSP_S_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_S.fd"<br></div><div> \
#CONFIG_FSP_T_FILE="../intel/fsp/denverton_ns/DENVERTON-NS_FSP_T.fd"<br></div><div> \
#CONFIG_FSP_CAR=y<br></div><div> <br></div><div> #Sample settings for microcode \
definitions.<br></div><div> \
#CONFIG_CPU_MICROCODE_HEADER_FILES="../intel/cpu/denverton_ns/microcode/microcode_blob.h"<br></div><div> \
#CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER=y<br></div><div> <br></div><div> \
Unfortunately all my harcuvar work has also been on a fairly old tree of \
coreboot.<br></div><div> <br></div><div> I'll give it a try on my Harcuvar if you \
don't make any progress, but it won't be until the weekend.<br></div><div> \
_______________________________________________<br></div><div> coreboot mailing list \
-- <a href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br></div><div> To \
unsubscribe send an email to <a \
href="mailto:coreboot-leave@coreboot.org">coreboot-leave@coreboot.org</a><br></div><p> \
</p></blockquote><div><p> <br></p></div><div><p> <br></p></div></div><p></p> \
<div>--------------------------------------------------------------<br></div><div> \
Intel Research and Development Ireland Limited<br></div><div> Registered in \
Ireland<br></div><div> Registered Office: Collinstown Industrial Park, Leixlip, \
County Kildare<br></div><div> Registered Number: 308263<br></div><p></p><p>This \
e-mail and any attachments may contain confidential material for the sole use of the \
intended recipient(s). Any review or distribution by others is strictly prohibited. \
If you are not the intended recipient, please contact the sender and delete all \
copies.<br></p><p><br></p></blockquote><div><br></div>
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