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List: linuxbios
Subject: Re: [coreboot] Test hardware initialization in emulator
From: Zoran Stojsavljevic <zoran.stojsavljevic () gmail ! com>
Date: 2016-08-25 5:24:16
Message-ID: CAGAf8LwzMH5oNPnYC+qX3yXxjUGLugf6dV+6U3GKg4F8v+xBMw () mail ! gmail ! com
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> Now I wanted to learn the "hard" part, mainly RAM initialization and PCI
enumeration.
Hard part, indeed, I should say. RAM init = MRC (INTEL IP), PCIe
enumeration, also IP, also part of FSP (there are open source alternatives
to PCIe enumeration). To really learn these, you should either have/obtain
source code, either to do reverse engineering.
None of these are easy. Maybe, upon getting HW, you should a bit explore
algorithms inside FSP using JTAG debugger (solely for the learning
experiences/purposes). Just a thought.
Zoran
On Wed, Aug 24, 2016 at 11:31 AM, Rishav Ambasta <kooolrishav@gmail.com>
wrote:
> I am exploring Coreboot.
> I had bought a Minnowboard, which will take some time to arrive.
> Meanwhile I wanted to carry out the learning on an emulator.
> I had compiled a ROM for QEMU and it ran successfully. I even tried with
> different payloads (which I hear is the easy part of the boot process)
> Now I wanted to learn the "hard" part, mainly RAM initialization and PCI
> enumeration.
>
> I had generated a ROM using the Minnowboard FSP, but I was not able to
> boot QEMU using it.
>
> Need suggestions on how can one, trace or at-least log the steps in the
> boot-block stage, ROM stage and RAM stage of Minnowboard on an Emulator.
>
> Regards,
> *Rishav Ambasta*
>
> *Save Plants, Save Life ...*
>
>
> --
> coreboot mailing list: coreboot@coreboot.org
> https://www.coreboot.org/mailman/listinfo/coreboot
>
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<div dir="ltr"><div><div><div>> Now I wanted to learn the "hard" part, \
mainly RAM initialization and PCI enumeration.<br><br></div>Hard part, indeed, I \
should say. RAM init = MRC (INTEL IP), PCIe enumeration, also IP, also part of FSP \
(there are open source alternatives to PCIe enumeration). To really learn these, you \
should either have/obtain source code, either to do reverse \
engineering.<br><br></div>None of these are easy. Maybe, upon getting HW, you should \
a bit explore algorithms inside FSP using JTAG debugger (solely for the learning \
experiences/purposes). Just a thought.<br><br></div>Zoran<br></div><div \
class="gmail_extra"><br><div class="gmail_quote">On Wed, Aug 24, 2016 at 11:31 AM, \
Rishav Ambasta <span dir="ltr"><<a href="mailto:kooolrishav@gmail.com" \
target="_blank">kooolrishav@gmail.com</a>></span> wrote:<br><blockquote \
class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc \
solid;padding-left:1ex"><div dir="ltr"><div><div><div><div>I am exploring \
Coreboot.<br>I had bought a Minnowboard, which will take some time to arrive. \
<br></div>Meanwhile I wanted to carry out the learning on an emulator.<br></div>I had \
compiled a ROM for QEMU and it ran successfully. I even tried with different payloads \
(which I hear is the easy part of the boot process)<br></div>Now I wanted to learn \
the "hard" part, mainly RAM initialization and PCI enumeration.<br><br>I \
had generated a ROM using the Minnowboard FSP, but I was not able to boot QEMU using \
it.<br><br></div><div>Need suggestions on how can one, trace or at-least log the \
steps in the boot-block stage, ROM stage and RAM stage of Minnowboard on an \
Emulator.<br></div><div><div><br clear="all"><div><div><div>Regards,<br><div \
data-smartmail="gmail_signature"><div dir="ltr"><font color="#444444" \
size="2"><b>Rishav Ambasta</b></font><div><blockquote style="margin:0px 0px 0px \
0.8ex;border-left:1px solid rgb(204,204,204);padding-left:1ex"><font color="#00ff00" \
size="1"><i style="background-color:rgb(255,255,255)">Save Plants, Save Life \
...</i></font></blockquote></div></div></div> </div></div></div></div></div></div>
<br>--<br>
coreboot mailing list: <a \
href="mailto:coreboot@coreboot.org">coreboot@coreboot.org</a><br> <a \
href="https://www.coreboot.org/mailman/listinfo/coreboot" rel="noreferrer" \
target="_blank">https://www.coreboot.org/<wbr>mailman/listinfo/coreboot</a><br></blockquote></div><br></div>
--
coreboot mailing list: coreboot@coreboot.org
https://www.coreboot.org/mailman/listinfo/coreboot
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