'[coreboot] How add or fix code for flashrom working on Abit BF6'

[prev in list] [next in list] [prev in thread] [next in thread] 

List:       linuxbios
Subject:    [coreboot] How add or fix code for flashrom working on Abit BF6
From:       "Gelip" <mrgelip () gmail ! com>
Date:       2013-12-26 18:39:16
Message-ID: 001201cf0269$c88d5180$0314a8c0 () bill
[Download RAW message or body]

[Attachment #2 (multipart/alternative)]

Checked by trial and error method that flashrom works when set PCI registers like \
this: ===============================
setpci -s 00:07.0 b0.l=e0000105
or
setpci -s 00:07.0 b2.w=e000
or
setpci -s 00:07.0 b3.b=e0

also work setpci -s 00:07.0 b2.w=8000 but e0 is from vendor bios.

I found this data in PCI config space device 'ISA Bridge' (offset b0) after boot PC \
on vendor bios like this: lspci -s 00:07.0 -xxx
Next compared this data with coreboot bios PCI config space for this device in offset \
b0.

Please help how fix code coreboot to make flashrom working?

P.S. Stefan Tauner wrote that this is coreboot code broken, not flashrom --> Link

[Attachment #5 (text/html)]

<!DOCTYPE HTML PUBLIC "-//W3C//DTD HTML 4.0 Transitional//EN">
<HTML><HEAD>
<META http-equiv=Content-Type content="text/html; charset=iso-8859-2">
<META content="MSHTML 6.00.2900.2180" name=GENERATOR>
<STYLE></STYLE>
</HEAD>
<BODY bgColor=#ffffff><FONT size=2>
<DIV><SPAN class="" lang=en id=result_box><FONT face="Courier New"><SPAN 
class=hps>Checked</SPAN> <SPAN class=hps>by trial</SPAN> <SPAN class=hps>and 
error</SPAN> method <SPAN class=hps>that</SPAN> <SPAN class=hps>flashrom</SPAN> 
<SPAN class=hps>works</SPAN> <SPAN class=hps>when set</SPAN> <SPAN 
class=hps>PCI</SPAN> <SPAN class=hps>registers</SPAN> like this<SPAN 
class="">:</SPAN></FONT></SPAN></DIV>
<DIV><SPAN class="" lang=en><SPAN class=""><FONT 
face="Courier New">===============================</FONT></SPAN></SPAN></DIV>
<DIV><FONT face="Courier New">setpci -s 00:07.0 b0.l=e0000105</FONT></DIV>
<DIV><FONT face="Courier New">or</FONT></DIV>
<DIV><FONT face="Courier New">setpci -s 00:07.0 b2.w=e000</FONT></DIV>
<DIV><FONT face="Courier New">or</FONT></DIV>
<DIV><FONT face="Courier New">setpci -s 00:07.0 b3.b=e0</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">also work setpci -s 00:07.0 b2.w=8000 but e0 is 
from vendor bios.</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">I found&nbsp;this data&nbsp;in PCI config space 
device 'ISA Bridge' (offset b0) after boot PC on vendor bios like 
this:</FONT></DIV>
<DIV><FONT face="Courier New">lspci -s 00:07.0 -xxx</FONT></DIV>
<DIV><FONT face="Courier New">Next compared this data with coreboot bios PCI 
config space for this device in offset b0.</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">Please help how fix code coreboot to make flashrom 
working?</FONT></DIV>
<DIV><FONT face="Courier New"></FONT>&nbsp;</DIV>
<DIV><FONT face="Courier New">P.S. Stefan Tauner wrote that this is coreboot 
code broken, not flashrom --&gt; </FONT><A 
href="http://www.flashrom.org/pipermail/flashrom/2013-December/011943.html"><FONT 
face="Courier New">Link</FONT></A></DIV></FONT></BODY></HTML>

-- 
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot

[prev in list] [next in list] [prev in thread] [next in thread] 