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List: linuxbios
Subject: Re: [coreboot] about Intel calpella board(I3+QM57)
From: "zxy__1127" <zxy__1127 () 163 ! com>
Date: 2011-02-28 4:18:41
Message-ID: 201102281218408595131 () 163 ! com
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Thanks for your info,I'll try to use SerialICE.
2011-02-28
zxy__1127
发件人： Peter Stuge
发送时间： 2011-02-28 10:45:40
收件人： coreboot@coreboot.org
抄送：
主题： Re: [coreboot] about Intel calpella board(I3+QM57)
Hello,
zxy__1127 wrote:
> I have worked on this board two weeks,now it can print from serial
> port,
This is a very important first step! Good news.
> and stop at ddr3 initialling in file romstage.c.
> I found it difficult to deal with it.
I can understand that. Memory initialization is the most complex task
in coreboot, and require many details to be exactly right, including
e.g. the sequence of steps and timing between steps.
> Is there anyone working on it?
My guess is no.
However, since you have the serial port working, you could try to use
SerialICE (see http://serialice.org/ ) to get a better understanding
of the operations done by the factory BIOS. This can help to create
the code needed in coreboot to bring up a board.
//Peter
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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<DIV><FONT face=Verdana color=#000080 size=2><FONT color=#000080>Thanks for your
info,I'll try to use SerialICE.</FONT><IMG
src="cid:__0@Foxmail.net"></FONT></DIV>
<DIV><FONT face=Verdana color=#000080 size=2></FONT> </DIV>
<DIV><FONT face=Verdana color=#000080 size=2></FONT> </DIV>
<DIV><FONT face=Verdana color=#c0c0c0 size=2>2011-02-28 </FONT></DIV><FONT
face=Verdana color=#000080 size=2>
<HR style="WIDTH: 122px; HEIGHT: 2px" align=left SIZE=2>
</FONT>
<DIV><FONT face=Verdana color=#c0c0c0 size=2><SPAN>zxy__1127</SPAN>
</FONT></DIV><FONT face=Verdana color=#000080 size=2>
<HR>
</FONT>
<DIV><FONT face=Verdana size=2><STRONG>发件人：</STRONG> Peter Stuge </FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>发送时间：</STRONG> 2011-02-28 10:45:40
</FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>收件人：</STRONG> coreboot@coreboot.org
</FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>抄送：</STRONG> </FONT></DIV>
<DIV><FONT face=Verdana size=2><STRONG>主题：</STRONG> Re: [coreboot] about Intel
calpella board(I3+QM57) </FONT></DIV>
<DIV><FONT face=Verdana size=2></FONT> </DIV>
<DIV><FONT face=Verdana size=2>
<DIV>Hello,</DIV>
<DIV> </DIV>
<DIV>zxy__1127 wrote:</DIV>
<DIV>> I have worked on this board two weeks,now it can print from serial</DIV>
<DIV>> port,</DIV>
<DIV> </DIV>
<DIV>This is a very important first step! Good news.</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>> and stop at ddr3 initialling in file romstage.c.</DIV>
<DIV>> I found it difficult to deal with it.</DIV>
<DIV> </DIV>
<DIV>I can understand that. Memory initialization is the most complex task</DIV>
<DIV>in coreboot, and require many details to be exactly right, including</DIV>
<DIV>e.g. the sequence of steps and timing between steps.</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>> Is there anyone working on it?</DIV>
<DIV> </DIV>
<DIV>My guess is no.</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>However, since you have the serial port working, you could try to use</DIV>
<DIV>SerialICE (see <A
href="http://serialice.org/ ) to get a better understand \
ing">http://serialice.org/ ) to get a better understanding</A></DIV>
<DIV>of the operations done by the factory BIOS. This can help to create</DIV>
<DIV>the code needed in coreboot to bring up a board.</DIV>
<DIV> </DIV>
<DIV> </DIV>
<DIV>//Peter</DIV>
<DIV> </DIV>
<DIV>-- </DIV>
<DIV>coreboot mailing list: coreboot@coreboot.org</DIV>
<DIV><A
href="http://www.coreboot.org/mailman/listinfo/coreboot">http://www.coreboot.org/mailman/listinfo/coreboot</A></DIV></FONT></DIV></BODY></HTML>
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--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
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