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List: linuxbios
Subject: [coreboot] [PATCH] __ROMCC__ ifdefs
From: Myles Watson <mylesgw () gmail ! com>
Date: 2009-10-30 13:24:51
Message-ID: 2831fecf0910300624r4a23f007p69347683e0070a96 () mail ! gmail ! com
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[Attachment #2 (multipart/alternative)]
I think it's time to separate the two meanings of __ROMCC__. Right now it
is used for:
1. Use simple functions and data types since we don't have RAM
2. Don't use prototypes, romcc doesn't support them.
Right now the patch creates __PRE_RAMINIT__
The name is not the most important part of the patch, and can easily be
changed.
Here are some of the suggestions so far:
__PRE_RAM__
__NO_RAM_YET__
__DURING_RAMINIT__
__USE_NO_RAM__
Unless it was obvious to me which meaning was the correct one for a file, I
added both for now.
Abuild tested.
Signed-off-by: Myles Watson <mylesgw@gmail.com>
Thanks,
Myles
[Attachment #5 (text/html)]
I think it's time to separate the two meanings of __ROMCC__. Right now it is \
used for:<br>1. Use simple functions and data types since we don't have RAM<br>2. \
Don't use prototypes, romcc doesn't support them.<br>
<br>Right now the patch creates __PRE_RAMINIT__<br><br>The name is not the most \
important part of the patch, and can easily be changed.<br><br>Here are some of the \
suggestions so far:<br>__PRE_RAM__<br>__NO_RAM_YET__<br> __DURING_RAMINIT__<br>
__USE_NO_RAM__<br><br>Unless it was obvious to me which meaning was the correct one \
for a file, I added both for now.<br><br>Abuild tested.<br><br>Signed-off-by: Myles \
Watson <<a href="mailto:mylesgw@gmail.com">mylesgw@gmail.com</a>><br> \
<br>Thanks,<br>Myles<br>
--001485f99caae432d2047726f371--
["romcc.diff" (text/x-patch)]
Index: svn/src/cpu/x86/smm/smmrelocate.S
===================================================================
--- svn.orig/src/cpu/x86/smm/smmrelocate.S
+++ svn/src/cpu/x86/smm/smmrelocate.S
@@ -22,7 +22,7 @@
#include <arch/asm.h>
// Make sure no stage 2 code is included:
-#define __ROMCC__
+#define __PRE_RAMINIT__
// FIXME: Is this piece of code southbridge specific, or
// can it be cleaned up so this include is not required?
Index: svn/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
+++ svn/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
@@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
Index: svn/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/amd/pistachio/cache_as_ram_auto.c
+++ svn/src/mainboard/amd/pistachio/cache_as_ram_auto.c
@@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
Index: svn/src/mainboard/amd/serengeti_cheetah/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/amd/serengeti_cheetah/apc_auto.c
+++ svn/src/mainboard/amd/serengeti_cheetah/apc_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
+++ svn/src/mainboard/amd/serengeti_cheetah/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
+++ svn/src/mainboard/amd/serengeti_cheetah_fam10/apc_auto.c
@@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
+++ svn/src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c
@@ -19,7 +19,7 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define SYSTEM_TYPE 0 /* SERVER */
//#define SYSTEM_TYPE 1 /* DESKTOP */
Index: svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/arima/hdama/cache_as_ram_auto.c
+++ svn/src/mainboard/arima/hdama/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <device/pci_def.h>
Index: svn/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
+++ svn/src/mainboard/asus/a8n_e/cache_as_ram_auto.c
@@ -22,7 +22,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
/* Used by it8712f_enable_serial(). */
#define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1)
Index: svn/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
+++ svn/src/mainboard/asus/a8v-e_se/cache_as_ram_auto.c
@@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
+++ svn/src/mainboard/asus/m2v-mx_se/cache_as_ram_auto.c
@@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/broadcom/blast/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/broadcom/blast/cache_as_ram_auto.c
+++ svn/src/mainboard/broadcom/blast/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define QRANK_DIMM_SUPPORT 1
Index: svn/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
+++ svn/src/mainboard/gigabyte/ga_2761gxdk/apc_auto.c
@@ -22,7 +22,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
+++ svn/src/mainboard/gigabyte/ga_2761gxdk/cache_as_ram_auto.c
@@ -22,7 +22,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/gigabyte/m57sli/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/gigabyte/m57sli/apc_auto.c
+++ svn/src/mainboard/gigabyte/m57sli/apc_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
+++ svn/src/mainboard/gigabyte/m57sli/cache_as_ram_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
+++ svn/src/mainboard/hp/dl145_g3/cache_as_ram_auto.c
@@ -26,7 +26,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/ibm/e325/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/ibm/e325/cache_as_ram_auto.c
+++ svn/src/mainboard/ibm/e325/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/ibm/e326/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/ibm/e326/cache_as_ram_auto.c
+++ svn/src/mainboard/ibm/e326/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/intel/d945gclf/auto.c
===================================================================
--- svn.orig/src/mainboard/intel/d945gclf/auto.c
+++ svn/src/mainboard/intel/d945gclf/auto.c
@@ -17,8 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-// __ROMCC__ means: use "unsigned" for device, not a struct.
-#define __ROMCC__
+// __PRE_RAMINIT__ means: use "unsigned" for device, not a struct.
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
@@ -220,10 +220,10 @@ static void early_ich7_init(void)
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
-// __ROMCC_ being set during CAR stage (in order to compile the
+// __PRE_RAMINIT__ being set during CAR stage (in order to compile the
// BSS free versions of the functions). Either rewrite the code
// to be always BSS free, or invent a flag that's better suited than
-// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+// __PRE_RAMINIT__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
Index: svn/src/mainboard/intel/eagleheights/auto.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/auto.c
+++ svn/src/mainboard/intel/eagleheights/auto.c
@@ -20,7 +20,7 @@
* MA 02110-1301 USA
*/
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <delay.h>
Index: svn/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
+++ svn/src/mainboard/iwill/dk8_htx/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
+++ svn/src/mainboard/iwill/dk8s2/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
+++ svn/src/mainboard/iwill/dk8x/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/kontron/986lcd-m/auto.c
===================================================================
--- svn.orig/src/mainboard/kontron/986lcd-m/auto.c
+++ svn/src/mainboard/kontron/986lcd-m/auto.c
@@ -19,8 +19,8 @@
* MA 02110-1301 USA
*/
-// __ROMCC__ means: use "unsigned" for device, not a struct.
-#define __ROMCC__
+// __PRE_RAMINIT__ means: use "unsigned" for device, not a struct.
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
@@ -359,10 +359,10 @@ static void early_ich7_init(void)
#include <cbmem.h>
// Now, this needs to be included because it relies on the symbol
-// __ROMCC_ being set during CAR stage (in order to compile the
+// __PRE_RAMINIT__ being set during CAR stage (in order to compile the
// BSS free versions of the functions). Either rewrite the code
// to be always BSS free, or invent a flag that's better suited than
-// __ROMCC__ to determine whether we're in ram init stage (stage 1)
+// __PRE_RAMINIT__ to determine whether we're in ram init stage (stage 1)
//
#include "lib/cbmem.c"
Index: svn/src/mainboard/kontron/kt690/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/kontron/kt690/cache_as_ram_auto.c
+++ svn/src/mainboard/kontron/kt690/cache_as_ram_auto.c
@@ -19,7 +19,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
Index: svn/src/mainboard/msi/ms7135/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/msi/ms7135/cache_as_ram_auto.c
+++ svn/src/mainboard/msi/ms7135/cache_as_ram_auto.c
@@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define SERIAL_DEV PNP_DEV(0x4e, W83627HF_SP1)
Index: svn/src/mainboard/msi/ms7260/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/msi/ms7260/apc_auto.c
+++ svn/src/mainboard/msi/ms7260/apc_auto.c
@@ -21,7 +21,7 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/msi/ms7260/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/msi/ms7260/cache_as_ram_auto.c
+++ svn/src/mainboard/msi/ms7260/cache_as_ram_auto.c
@@ -21,7 +21,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
// #define CACHE_AS_RAM_ADDRESS_DEBUG 1
// #define DEBUG_SMBUS 1
Index: svn/src/mainboard/msi/ms9185/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/msi/ms9185/cache_as_ram_auto.c
+++ svn/src/mainboard/msi/ms9185/cache_as_ram_auto.c
@@ -24,7 +24,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/msi/ms9282/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/msi/ms9282/cache_as_ram_auto.c
+++ svn/src/mainboard/msi/ms9282/cache_as_ram_auto.c
@@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/newisys/khepri/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/newisys/khepri/cache_as_ram_auto.c
+++ svn/src/mainboard/newisys/khepri/cache_as_ram_auto.c
@@ -4,7 +4,7 @@
* Additional (C) 2007 coresystems GmbH
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/nvidia/l1_2pvv/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/nvidia/l1_2pvv/apc_auto.c
+++ svn/src/mainboard/nvidia/l1_2pvv/apc_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
+++ svn/src/mainboard/nvidia/l1_2pvv/cache_as_ram_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
+++ svn/src/mainboard/sunw/ultra40/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define K8_ALLOCATE_IO_RANGE 1
Index: svn/src/mainboard/supermicro/h8dme/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dme/apc_auto.c
+++ svn/src/mainboard/supermicro/h8dme/apc_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
+++ svn/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
@@ -17,7 +17,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/supermicro/h8dmr/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr/apc_auto.c
+++ svn/src/mainboard/supermicro/h8dmr/apc_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
+++ svn/src/mainboard/supermicro/h8dmr/cache_as_ram_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
+++ svn/src/mainboard/supermicro/h8dmr_fam10/apc_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c
+++ svn/src/mainboard/supermicro/h8dmr_fam10/cache_as_ram_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
+++ svn/src/mainboard/technexion/tim5690/cache_as_ram_auto.c
@@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
Index: svn/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
+++ svn/src/mainboard/technexion/tim8690/cache_as_ram_auto.c
@@ -18,7 +18,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define K8_SET_FIDVID 1
Index: svn/src/mainboard/tyan/s2735/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2735/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2735/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s2850/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2850/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2850/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s2875/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2875/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2875/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s2880/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2880/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2880/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s2881/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2881/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2881/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define QRANK_DIMM_SUPPORT 1
Index: svn/src/mainboard/tyan/s2882/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2882/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2882/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s2885/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2885/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2885/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s2891/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2891/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2891/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
//used by raminit
#define QRANK_DIMM_SUPPORT 1
Index: svn/src/mainboard/tyan/s2892/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2892/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2892/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define QRANK_DIMM_SUPPORT 1
Index: svn/src/mainboard/tyan/s2895/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2895/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2895/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define K8_ALLOCATE_IO_RANGE 1
Index: svn/src/mainboard/tyan/s2895/failover.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2895/failover.c
+++ svn/src/mainboard/tyan/s2895/failover.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s2912/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2912/apc_auto.c
+++ svn/src/mainboard/tyan/s2912/apc_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/tyan/s2912/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2912/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2912/cache_as_ram_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/tyan/s2912_fam10/apc_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2912_fam10/apc_auto.c
+++ svn/src/mainboard/tyan/s2912_fam10/apc_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s2912_fam10/cache_as_ram_auto.c
@@ -20,7 +20,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
Index: svn/src/mainboard/tyan/s4880/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s4880/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s4880/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/tyan/s4882/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/tyan/s4882/cache_as_ram_auto.c
+++ svn/src/mainboard/tyan/s4882/cache_as_ram_auto.c
@@ -1,5 +1,5 @@
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <string.h>
Index: svn/src/mainboard/via/epia-m700/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/mainboard/via/epia-m700/cache_as_ram_auto.c
+++ svn/src/mainboard/via/epia-m700/cache_as_ram_auto.c
@@ -23,7 +23,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/northbridge/via/vx800/examples/cache_as_ram_auto.c
===================================================================
--- svn.orig/src/northbridge/via/vx800/examples/cache_as_ram_auto.c
+++ svn/src/northbridge/via/vx800/examples/cache_as_ram_auto.c
@@ -19,7 +19,7 @@
*/
#define ASSEMBLY 1
-#define __ROMCC__
+#define __PRE_RAMINIT__
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
Index: svn/src/arch/i386/include/arch/cpu.h
===================================================================
--- svn.orig/src/arch/i386/include/arch/cpu.h
+++ svn/src/arch/i386/include/arch/cpu.h
@@ -104,7 +104,7 @@ static inline unsigned int cpuid_edx(uns
#define X86_VENDOR_SIS 10
#define X86_VENDOR_UNKNOWN 0xff
-#if !defined( __ROMCC__ ) && defined( __GNUC__)
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__) && defined( __GNUC__)
#include <device/device.h>
Index: svn/src/arch/i386/include/arch/hlt.h
===================================================================
--- svn.orig/src/arch/i386/include/arch/hlt.h
+++ svn/src/arch/i386/include/arch/hlt.h
@@ -1,7 +1,7 @@
#ifndef ARCH_HLT_H
#define ARCH_HLT_H
-#if defined( __ROMCC__) && !defined(__GNUC__)
+#if defined( __ROMCC__) && !defined(__PRE_RAMINIT__) && !defined(__GNUC__)
static void hlt(void)
{
__builtin_hlt();
Index: svn/src/arch/i386/include/arch/io.h
===================================================================
--- svn.orig/src/arch/i386/include/arch/io.h
+++ svn/src/arch/i386/include/arch/io.h
@@ -9,7 +9,7 @@
* (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing"
* versions of the single-IO instructions (inb_p/inw_p/..).
*/
-#if defined( __ROMCC__ ) && !defined (__GNUC__)
+#if defined( __ROMCC__ ) && !defined (__GNUC__)
static inline void outb(uint8_t value, uint16_t port)
{
__builtin_outb(value, port);
Index: svn/src/arch/i386/lib/console_print.c
===================================================================
--- svn.orig/src/arch/i386/lib/console_print.c
+++ svn/src/arch/i386/lib/console_print.c
@@ -66,7 +66,7 @@ static void __console_tx_string(int logl
* set in some auto.c files to trigger the simple device_t version to be used.
* So __GNUCC__ does the right thing here.
*/
-#if defined (__GNUCC__)
+#if defined (__ROMCC__)
#define STATIC
#else
#define STATIC static
Index: svn/src/cpu/amd/dualcore/dualcore_id.c
===================================================================
--- svn.orig/src/cpu/amd/dualcore/dualcore_id.c
+++ svn/src/cpu/amd/dualcore/dualcore_id.c
@@ -2,7 +2,7 @@
#include <arch/cpu.h>
#include <cpu/amd/dualcore.h>
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
#include <cpu/amd/model_fxx_msr.h>
#endif
Index: svn/src/cpu/amd/microcode/microcode.c
===================================================================
--- svn.orig/src/cpu/amd/microcode/microcode.c
+++ svn/src/cpu/amd/microcode/microcode.c
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __ROMCC__
+#ifndef __PRE_RAMINIT__
#include <stdint.h>
#include <console/console.h>
Index: svn/src/cpu/amd/model_10xxx/apic_timer.c
===================================================================
--- svn.orig/src/cpu/amd/model_10xxx/apic_timer.c
+++ svn/src/cpu/amd/model_10xxx/apic_timer.c
@@ -23,8 +23,8 @@
#include <cpu/x86/lapic.h>
/* NOTE: We use the APIC TIMER register is to hold flags for AP init during
- * pre-memory init (ROMCC). Don't use init_timer() and udelay is redirected
- * to udelay_tsc().
+ * pre-memory init (__PRE_RAMINIT__). Don't use init_timer() and udelay is
+ * redirected to udelay_tsc().
*/
Index: svn/src/cpu/amd/model_10xxx/update_microcode.c
===================================================================
--- svn.orig/src/cpu/amd/model_10xxx/update_microcode.c
+++ svn/src/cpu/amd/model_10xxx/update_microcode.c
@@ -18,7 +18,7 @@
*/
-#ifndef __ROMCC__
+#ifndef __PRE_RAMINIT__
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
@@ -29,7 +29,7 @@
static const u8 microcode_updates[] __attribute__ ((aligned(16))) = {
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
/* From the Revision Guide :
* Equivalent Processor Table for AMD Family 10h Processors
Index: svn/src/cpu/amd/quadcore/quadcore_id.c
===================================================================
--- svn.orig/src/cpu/amd/quadcore/quadcore_id.c
+++ svn/src/cpu/amd/quadcore/quadcore_id.c
@@ -20,7 +20,7 @@
#include <arch/cpu.h>
#include <cpu/amd/quadcore.h>
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
#include <cpu/amd/model_10xxx_msr.h>
#endif
Index: svn/src/include/assert.h
===================================================================
--- svn.orig/src/include/assert.h
+++ svn/src/include/assert.h
@@ -24,7 +24,7 @@
// ROMCC doesn't support __FILE__ or __LINE__ :^{
#if CONFIG_DEBUG
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
#define ASSERT(x) { if (!(x)) die("ASSERT failure!\r\n"); }
#else
#define ASSERT(x) { \
@@ -39,7 +39,7 @@
#define ASSERT(x) { }
#endif
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
#define BUG() { die("BUG encountered: system halted\r\n"); }
#else
#define BUG() { \
Index: svn/src/include/cpu/amd/dualcore.h
===================================================================
--- svn.orig/src/include/cpu/amd/dualcore.h
+++ svn/src/include/cpu/amd/dualcore.h
@@ -15,7 +15,7 @@ struct node_core_id {
struct node_core_id get_node_core_id(unsigned int nb_cfg_54);
#endif
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
struct device;
unsigned get_apicid_base(unsigned ioapic_num);
void amd_sibling_init(struct device *cpu);
Index: svn/src/include/cpu/amd/model_fxx_rev.h
===================================================================
--- svn.orig/src/include/cpu/amd/model_fxx_rev.h
+++ svn/src/include/cpu/amd/model_fxx_rev.h
@@ -49,7 +49,7 @@ static inline int is_cpu_e0(void)
}
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
static int is_e0_later_in_bsp(int nodeid)
{
uint32_t val;
@@ -96,7 +96,7 @@ static inline int is_cpu_pre_f2(void)
return (cpuid_eax(1) & 0xfff0f) < 0x40f02;
}
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
//AMD_F0_SUPPORT
static int is_cpu_f0_in_bsp(int nodeid)
{
Index: svn/src/include/cpu/amd/mtrr.h
===================================================================
--- svn.orig/src/include/cpu/amd/mtrr.h
+++ svn/src/include/cpu/amd/mtrr.h
@@ -31,7 +31,7 @@
#define TOP_MEM_MASK 0x007fffff
#define TOP_MEM_MASK_KB (TOP_MEM_MASK >> 10)
-#if !defined( __ROMCC__ ) && !defined (ASSEMBLY)
+#if !defined( __ROMCC__ ) && !defined (ASSEMBLY) && !defined(__PRE_RAMINIT__)
void amd_setup_mtrrs(void);
#endif /* __ROMCC__ */
Index: svn/src/include/cpu/amd/quadcore.h
===================================================================
--- svn.orig/src/include/cpu/amd/quadcore.h
+++ svn/src/include/cpu/amd/quadcore.h
@@ -34,7 +34,7 @@ struct node_core_id {
struct node_core_id get_node_core_id(u32 nb_cfg_54);
#endif
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
struct device;
u32 get_apicid_base(u32 ioapic_num);
void amd_sibling_init(struct device *cpu);
Index: svn/src/include/cpu/x86/cache.h
===================================================================
--- svn.orig/src/include/cpu/x86/cache.h
+++ svn/src/include/cpu/x86/cache.h
@@ -41,7 +41,7 @@ static inline void disable_cache(void)
wbinvd();
}
-#if !defined( __ROMCC__) && defined (__GNUC__)
+#if !defined( __ROMCC__) && !defined(__PRE_RAMINIT__) && defined (__GNUC__)
void x86_enable_cache(void);
#endif /* !__ROMCC__ */
Index: svn/src/include/cpu/x86/lapic.h
===================================================================
--- svn.orig/src/include/cpu/x86/lapic.h
+++ svn/src/include/cpu/x86/lapic.h
@@ -68,7 +68,7 @@ static inline __attribute__((always_inli
}
#endif
-#if ! defined (__ROMCC__)
+#if ! defined (__ROMCC__) && !defined(__PRE_RAMINIT__)
#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned \
long)(v),(ptr),sizeof(*(ptr))))
@@ -157,6 +157,6 @@ int start_cpu(struct device *cpu);
#endif /* CONFIG_SMP */
-#endif /* !__ROMCC__ */
+#endif /* !__ROMCC__ && !__PRE_RAMINIT__ */
#endif /* CPU_X86_LAPIC_H */
Index: svn/src/include/cpu/x86/msr.h
===================================================================
--- svn.orig/src/include/cpu/x86/msr.h
+++ svn/src/include/cpu/x86/msr.h
@@ -1,7 +1,7 @@
#ifndef CPU_X86_MSR_H
#define CPU_X86_MSR_H
-#if defined( __ROMCC__) && !defined (__GNUC__)
+#if defined( __ROMCC__)
typedef __builtin_msr_t msr_t;
@@ -43,7 +43,7 @@ static inline void wrmsr(unsigned index,
);
}
-#endif /* ROMCC__ && !__GNUC__ */
+#endif /* __ROMCC__ */
#endif /* CPU_X86_MSR_H */
Index: svn/src/include/cpu/x86/mtrr.h
===================================================================
--- svn.orig/src/include/cpu/x86/mtrr.h
+++ svn/src/include/cpu/x86/mtrr.h
@@ -32,7 +32,7 @@
#define MTRRfix4K_F8000_MSR 0x26f
-#if !defined(__ROMCC__) && !defined (ASSEMBLY)
+#if !defined(__ROMCC__) && !defined (ASSEMBLY) && !defined(__PRE_RAMINIT__)
#include <device/device.h>
Index: svn/src/include/cpu/x86/tsc.h
===================================================================
--- svn.orig/src/include/cpu/x86/tsc.h
+++ svn/src/include/cpu/x86/tsc.h
@@ -17,7 +17,7 @@ static tsc_t rdtsc(void)
return res;
}
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined (__PRE_RAMINIT__)
static inline unsigned long long rdtscll(void)
{
unsigned long long val;
Index: svn/src/include/stdlib.h
===================================================================
--- svn.orig/src/include/stdlib.h
+++ svn/src/include/stdlib.h
@@ -11,7 +11,7 @@
#define MIN(a,b) ((a) < (b) ? (a) : (b))
#define MAX(a,b) ((a) > (b) ? (a) : (b))
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
void *malloc(size_t size);
void free(void *ptr);
#endif
Index: svn/src/include/string.h
===================================================================
--- svn.orig/src/include/string.h
+++ svn/src/include/string.h
@@ -8,7 +8,7 @@ void *memcpy(void *dest, const void *src
void *memmove(void *dest, const void *src, size_t n);
void *memset(void *s, int c, size_t n);
int memcmp(const void *s1, const void *s2, size_t n);
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
int sprintf(char * buf, const char *fmt, ...);
#endif
@@ -41,7 +41,7 @@ static inline char *strchr(const char *s
return 0;
}
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
static inline char *strdup(const char *s)
{
size_t sz = strlen(s) + 1;
Index: svn/src/lib/cbmem.c
===================================================================
--- svn.orig/src/lib/cbmem.c
+++ svn/src/lib/cbmem.c
@@ -45,7 +45,7 @@ struct cbmem_entry {
u64 size;
} __attribute__((packed));
-#ifndef __ROMCC__
+#ifndef __PRE_RAMINIT__
struct cbmem_entry *bss_cbmem_toc;
#endif
@@ -64,7 +64,7 @@ void cbmem_init(u64 baseaddr, u64 size)
struct cbmem_entry *cbmem_toc;
cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
-#ifndef __ROMCC__
+#ifndef __PRE_RAMINIT__
bss_cbmem_toc = cbmem_toc;
#endif
@@ -91,7 +91,7 @@ int cbmem_reinit(u64 baseaddr)
cbmem_toc = (struct cbmem_entry *)(unsigned long)baseaddr;
debug("Re-Initializing CBMEM area to 0x%lx\n", (unsigned long)baseaddr);
-#ifndef __ROMCC__
+#ifndef __PRE_RAMINIT__
bss_cbmem_toc = cbmem_toc;
#endif
@@ -102,7 +102,7 @@ void *cbmem_add(u32 id, u64 size)
{
struct cbmem_entry *cbmem_toc;
int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
@@ -158,7 +158,7 @@ void *cbmem_find(u32 id)
{
struct cbmem_entry *cbmem_toc;
int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
@@ -175,7 +175,7 @@ void *cbmem_find(u32 id)
return (void *)NULL;
}
-#ifndef __ROMCC__
+#ifndef __PRE_RAMINIT__
#if CONFIG_HAVE_ACPI_RESUME
extern u8 acpi_slp_type;
#endif
@@ -199,12 +199,12 @@ void cbmem_initialize(void)
cbmem_arch_init();
}
-#ifndef __ROMCC__
+#ifndef __PRE_RAMINIT__
void cbmem_list(void)
{
struct cbmem_entry *cbmem_toc;
int i;
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
cbmem_toc = (struct cbmem_entry *)(get_top_of_ram() - HIGH_MEMORY_SIZE);
#else
cbmem_toc = bss_cbmem_toc;
Index: svn/src/lib/usbdebug_direct.c
===================================================================
--- svn.orig/src/lib/usbdebug_direct.c
+++ svn/src/lib/usbdebug_direct.c
@@ -19,7 +19,7 @@
/*
* 2006.12.10 yhlu moved it to corbeoot and use struct instead
*/
-#ifndef __ROMCC__
+#if !defined(__ROMCC__)
#include <console/console.h>
#else
#if CONFIG_USE_PRINTK_IN_CAR==0
Index: svn/src/mainboard/dell/s1850/reset.c
===================================================================
--- svn.orig/src/mainboard/dell/s1850/reset.c
+++ svn/src/mainboard/dell/s1850/reset.c
@@ -2,7 +2,7 @@
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/pci.h>
#define PCI_ID(VENDOR_ID, DEVICE_ID) \
((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
Index: svn/src/mainboard/intel/eagleheights/reset.c
===================================================================
--- svn.orig/src/mainboard/intel/eagleheights/reset.c
+++ svn/src/mainboard/intel/eagleheights/reset.c
@@ -22,7 +22,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Index: svn/src/mainboard/intel/jarrell/reset.c
===================================================================
--- svn.orig/src/mainboard/intel/jarrell/reset.c
+++ svn/src/mainboard/intel/jarrell/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Index: svn/src/mainboard/supermicro/x6dai_g/reset.c
===================================================================
--- svn.orig/src/mainboard/supermicro/x6dai_g/reset.c
+++ svn/src/mainboard/supermicro/x6dai_g/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Index: svn/src/mainboard/supermicro/x6dhe_g/reset.c
===================================================================
--- svn.orig/src/mainboard/supermicro/x6dhe_g/reset.c
+++ svn/src/mainboard/supermicro/x6dhe_g/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Index: svn/src/mainboard/supermicro/x6dhe_g2/reset.c
===================================================================
--- svn.orig/src/mainboard/supermicro/x6dhe_g2/reset.c
+++ svn/src/mainboard/supermicro/x6dhe_g2/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Index: svn/src/mainboard/supermicro/x6dhr_ig/reset.c
===================================================================
--- svn.orig/src/mainboard/supermicro/x6dhr_ig/reset.c
+++ svn/src/mainboard/supermicro/x6dhr_ig/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Index: svn/src/mainboard/supermicro/x6dhr_ig2/reset.c
===================================================================
--- svn.orig/src/mainboard/supermicro/x6dhr_ig2/reset.c
+++ svn/src/mainboard/supermicro/x6dhr_ig2/reset.c
@@ -1,7 +1,7 @@
#include <arch/io.h>
#include <device/pci_def.h>
#include <device/pci_ids.h>
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
Index: svn/src/northbridge/amd/amdfam10/amdfam10.h
===================================================================
--- svn.orig/src/northbridge/amd/amdfam10/amdfam10.h
+++ svn/src/northbridge/amd/amdfam10/amdfam10.h
@@ -956,7 +956,7 @@ that are corresponding to 0x01, 0x02, 0x
#include "amdfam10_nums.h"
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
#if NODE_NUMS==64
#define NODE_PCI(x, fn) \
((x<32)?(PCI_DEV(CONFIG_CBB,(CONFIG_CDB+x),fn)):(PCI_DEV((CONFIG_CBB-1),(CONFIG_CDB+x-32),fn)))
#else
@@ -1086,7 +1086,7 @@ struct sys_info {
#if CONFIG_AMDMCT == 0
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
static void soft_reset(void);
#endif
static void wait_all_core0_mem_trained(struct sys_info *sysinfo)
@@ -1131,7 +1131,7 @@ static void wait_all_core0_mem_trained(s
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); \
print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\n"); #else
printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
@@ -1148,7 +1148,7 @@ static void wait_all_core0_mem_trained(s
}
}
if(needs_reset) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
print_debug("mem trained failed\n");
soft_reset();
#else
Index: svn/src/northbridge/amd/amdfam10/amdfam10_conf.c
===================================================================
--- svn.orig/src/northbridge/amd/amdfam10/amdfam10_conf.c
+++ svn/src/northbridge/amd/amdfam10/amdfam10_conf.c
@@ -17,7 +17,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
typedef struct sys_info sys_info_conf_t;
#else
typedef struct amdfam10_sysconf_t sys_info_conf_t;
@@ -32,7 +32,7 @@ static struct dram_base_mask_t get_dram_
{
device_t dev;
struct dram_base_mask_t d;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = PCI_DEV(CONFIG_CBB, CONFIG_CDB, 1);
#else
dev = __f1_dev[0];
@@ -88,7 +88,7 @@ static void set_dram_base_mask(u32 nodei
#endif
for(i=0;i<nodes;i++) {
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -108,7 +108,7 @@ static void set_dram_base_mask(u32 nodei
#endif
}
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(nodeid, 1);
#else
dev = __f1_dev[nodeid];
@@ -122,7 +122,7 @@ static void set_dram_base_mask(u32 nodei
static void set_DctSelBaseAddr(u32 i, u32 sel_m)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@@ -139,7 +139,7 @@ static void set_DctSelBaseAddr(u32 i, u3
static u32 get_DctSelBaseAddr(u32 i)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@@ -156,7 +156,7 @@ static u32 get_DctSelBaseAddr(u32 i)
static void set_DctSelHiEn(u32 i, u32 val)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@@ -172,7 +172,7 @@ static void set_DctSelHiEn(u32 i, u32 va
static u32 get_DctSelHiEn(u32 i)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@@ -187,7 +187,7 @@ static u32 get_DctSelHiEn(u32 i)
static void set_DctSelBaseOffset(u32 i, u32 sel_off_m)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@@ -203,7 +203,7 @@ static void set_DctSelBaseOffset(u32 i,
static u32 get_DctSelBaseOffset(u32 i)
{
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 2);
#else
dev = __f2_dev[i];
@@ -264,7 +264,7 @@ static u32 hoist_memory(u32 hole_startk,
d = get_dram_base_mask(i);
d.mask += (carry_over>>9);
set_dram_base_mask(i,d, nodes);
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -330,7 +330,7 @@ static void set_addr_map_reg_4_6_in_one_
index_max = busn_max>>2; dest_max = busn_max - (index_max<<2);
// three case: index_min==index_max, index_min+1=index_max; index_min+1<index_max
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(nodeid, 1);
#else
dev = __f1_dev[nodeid];
@@ -393,7 +393,7 @@ static void set_config_map_reg(u32 nodei
#endif
tempreg = 3 | ((nodeid&0xf)<<4) | ((nodeid & 0x30)<<(12-4))|(linkn<<8)|((busn_min \
& 0xff)<<16)|((busn_max&0xff)<<24); for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -433,7 +433,7 @@ static void clear_config_map_reg(u32 nod
if(ht_c_index<4) {
#endif
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -480,7 +480,7 @@ static u32 check_segn(device_t dev, u32
}
#endif
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
static void set_ht_c_io_addr_reg(u32 nodeid, u32 linkn, u32 ht_c_index,
u32 io_min, u32 io_max, u32 nodes)
{
@@ -494,7 +494,7 @@ static void set_ht_c_io_addr_reg(u32 nod
/* io range allocation */
tempreg = (nodeid&0xf) | ((nodeid & 0x30)<<(8-4)) | (linkn<<4) | \
((io_max&0xf0)<<(12-4)); //limit for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -503,7 +503,7 @@ static void set_ht_c_io_addr_reg(u32 nod
}
tempreg = 3 /*| ( 3<<4)*/ | ((io_min&0xf0)<<(12-4)); //base :ISA and VGA ?
for(i=0; i<nodes; i++){
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -546,7 +546,7 @@ static void clear_ht_c_io_addr_reg(u32 n
#endif
/* io range allocation */
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -584,7 +584,7 @@ static void re_set_all_config_map_reg(u3
for(ht_c_index=1;ht_c_index<4; ht_c_index++) {
u32 i;
for(i=0; i<nodes; i++) {
- #if defined(__ROMCC__)
+ #if defined(__PRE_RAMINIT__)
dev = NODE_PCI(i, 1);
#else
dev = __f1_dev[i];
@@ -664,7 +664,7 @@ static void set_BusSegmentEn(u32 node,
u32 dword;
device_t dev;
-#if defined(__ROMCC__)
+#if defined(__PRE_RAMINIT__)
dev = NODE_PCI(node, 0);
#else
dev = __f0_dev[node];
@@ -677,7 +677,7 @@ static void set_BusSegmentEn(u32 node,
#endif
}
-#if !defined(__ROMCC__)
+#if !defined(__PRE_RAMINIT__)
static u32 get_io_addr_index(u32 nodeid, u32 linkn)
{
u32 index;
Index: svn/src/northbridge/amd/amdk8/amdk8_f.h
===================================================================
--- svn.orig/src/northbridge/amd/amdk8/amdk8_f.h
+++ svn/src/northbridge/amd/amdk8/amdk8_f.h
@@ -518,7 +518,7 @@ struct sys_info {
uint32_t sbbusn;
} __attribute__((packed));
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
static void soft_reset(void);
#else
void hard_reset(void);
@@ -562,7 +562,7 @@ static void wait_all_core0_mem_trained(s
}
for(i=0; i<sysinfo->nodes; i++) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
print_debug("mem_trained["); print_debug_hex8(i); print_debug("]="); \
print_debug_hex8(sysinfo->mem_trained[i]); print_debug("\r\n"); #else
printk_debug("mem_trained[%02x]=%02x\n", i, sysinfo->mem_trained[i]);
@@ -579,7 +579,7 @@ static void wait_all_core0_mem_trained(s
}
}
if(needs_reset) {
-#ifdef __ROMCC__
+#ifdef __PRE_RAMINIT__
print_debug("mem trained failed\r\n");
soft_reset();
#else
Index: svn/src/northbridge/via/cn700/cn700.h
===================================================================
--- svn.orig/src/northbridge/via/cn700/cn700.h
+++ svn/src/northbridge/via/cn700/cn700.h
@@ -18,7 +18,7 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __ROMCC__
+#if !defined (__ROMCC__) && !defined (__PRE_RAMINIT__)
static void cn700_noop()
{
}
Index: svn/src/southbridge/amd/cs5530/cs5530.h
===================================================================
--- svn.orig/src/southbridge/amd/cs5530/cs5530.h
+++ svn/src/southbridge/amd/cs5530/cs5530.h
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
#define SOUTHBRIDGE_AMD_CS5530_CS5530_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
#include "chip.h"
void cs5530_enable(device_t dev);
#endif
Index: svn/src/southbridge/intel/i82371eb/i82371eb.h
===================================================================
--- svn.orig/src/southbridge/intel/i82371eb/i82371eb.h
+++ svn/src/southbridge/intel/i82371eb/i82371eb.h
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
#define SOUTHBRIDGE_INTEL_I82371EB_I82371EB_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
#include "chip.h"
void i82371eb_enable(device_t dev);
void i82371eb_hard_reset(void);
Index: svn/src/southbridge/intel/i82801ca/i82801ca.h
===================================================================
--- svn.orig/src/southbridge/intel/i82801ca/i82801ca.h
+++ svn/src/southbridge/intel/i82801ca/i82801ca.h
@@ -1,7 +1,7 @@
#ifndef I82801CA_H
#define I82801CA_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
#include "chip.h"
extern void i82801ca_enable(device_t dev);
#endif
Index: svn/src/southbridge/intel/i82801gx/i82801gx.h
===================================================================
--- svn.orig/src/southbridge/intel/i82801gx/i82801gx.h
+++ svn/src/southbridge/intel/i82801gx/i82801gx.h
@@ -41,7 +41,7 @@
/* __ROMCC__ is set by auto.c to make sure
* none of the stage2 data structures are included.
*/
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
#include "chip.h"
extern void i82801gx_enable(device_t dev);
#endif
Index: svn/src/southbridge/intel/i82801xx/i82801xx.h
===================================================================
--- svn.orig/src/southbridge/intel/i82801xx/i82801xx.h
+++ svn/src/southbridge/intel/i82801xx/i82801xx.h
@@ -21,7 +21,7 @@
#ifndef SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
#define SOUTHBRIDGE_INTEL_I82801XX_I82801XX_H
-#ifndef __ROMCC__
+#if !defined( __ROMCC__ ) && !defined(__PRE_RAMINIT__)
#include "chip.h"
extern void i82801xx_enable(device_t dev);
#endif
Index: svn/src/mainboard/intel/xe7501devkit/auto.c
===================================================================
--- svn.orig/src/mainboard/intel/xe7501devkit/auto.c
+++ svn/src/mainboard/intel/xe7501devkit/auto.c
@@ -1,4 +1,5 @@
#define ASSEMBLY 1
+#define __PRE_RAMINIT__
#include <stdint.h>
#include <device/pci_def.h>
--
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