[prev in list] [next in list] [prev in thread] [next in thread] 

List:       linux-wireless
Subject:    Re: [REGRESSION] Recent swiotlb DMA_FROM_DEVICE fixes break ath9k-based AP
From:       Halil Pasic <pasic () linux ! ibm ! com>
Date:       2022-03-30 12:11:54
Message-ID: 20220330141154.2ed284f1.pasic () linux ! ibm ! com
[Download RAW message or body]

On Mon, 28 Mar 2022 08:37:23 +0200
Christoph Hellwig <hch@lst.de> wrote:

> On Fri, Mar 25, 2022 at 11:46:09AM -0700, Linus Torvalds wrote:
> > I think my list of three different sync cases (not just two! It's not
> > just about whether to sync for the CPU or the device, it's also about
> > what direction the data itself is taking) is correct.
> > 
> > But maybe I'm wrong.  
> 
> At the high level you are correct.  It is all about which direction
> the data is taking.  That is the direction argument that all the
> map/unmap/sync call take.  The sync calls then just toggle the ownership.
> You seem to hate that ownership concept, but I don't see how things
> could work without that ownership concept as we're going to be in
> trouble without having that.  And yes, a peek operation could work in
> some cases, but it would have to be at the cache line granularity.
> 
> arch/arc/mm/dma.c has a really good comment how these transfers relate
> to actual cache operations btw>
> 
>  *
>  *          |   map          ==  for_device     |   unmap     ==  for_cpu
>  *          |----------------------------------------------------------------
>  * TO_DEV   |   writeback        writeback      |   none          none
>  * FROM_DEV |   invalidate       invalidate     |   invalidate*	  invalidate*

Very interesting! Does that mean that

memset(buf, 0, size);
dma_map(buf, size, FROM_DEVICE)
device does a partial write
dma_unmap(buf, size, FROM_DEVICE)

may boil down to being the same as without the memset(), because the
effect of the memset() may get thrown away by the cache invalidate?

That is in this scenario we could actually leak the original content of
the buffer if we have a non-dma-coherent cache?

Regards,
Halil 

>  * BIDIR    |   writeback+inv    writeback+inv  |   invalidate    invalidate
>  *
>  *     [*] needed for CPU speculative prefetches

[prev in list] [next in list] [prev in thread] [next in thread]