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List: linux-spi
Subject: [PATCH v2 1/4] dt-bindings: spi: snps,dw-apb-ssi: document Microsemi integration
From: Alexandre Belloni <alexandre.belloni () bootlin ! com>
Date: 2018-07-27 12:05:32
Message-ID: 20180727120535.16504-2-alexandre.belloni () bootlin ! com
[Download RAW message or body]
The integration of the Designware SPI controller on Microsemi SoCs requires
an extra register set to be able to give the IP control of the SPI
interface.
Cc: Rob Herring <robh+dt@kernel.org>
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
---
Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt \
b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt index \
204b311e0400..d97b9fc4c1cb 100644
--- a/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
+++ b/Documentation/devicetree/bindings/spi/snps,dw-apb-ssi.txt
@@ -1,8 +1,9 @@
Synopsys DesignWare AMBA 2.0 Synchronous Serial Interface.
Required properties:
-- compatible : "snps,dw-apb-ssi"
-- reg : The register base for the controller.
+- compatible : "snps,dw-apb-ssi" or "mscc,<soc>-spi"
+- reg : The register base for the controller. For "mscc,<soc>-spi", a second
+ register set is required (named ICPU_CFG:SPI_MST)
- interrupts : One interrupt, used by the controller.
- #address-cells : <1>, as required by generic SPI binding.
- #size-cells : <0>, also as required by generic SPI binding.
--
2.18.0
--
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