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List: linux-smp
Subject: WARNING: unexpected IO-APIC on boot RedHat kernel 2.4.20-28.7smp
From: Brian McEntire <brianm () fsg1 ! nws ! noaa ! gov>
Date: 2004-03-04 13:29:26
Message-ID: Pine.LNX.4.44.0403040815210.6295-100000 () fsg1 ! nws ! noaa ! gov
[Download RAW message or body]
Hello!
Perhaps the recommendation will be 'upgrade to a newer kernel' but just
incase someone is interested in this error I'm sending this e-mail.
I have three IBM IntelliStation Z Pro workstations that are all
displaying random lock-ups. These systems are all Dual 2.4 GHz Xeons with
2 GB RAM.
/var/log/messages contains the following messages:
kernel: WARNING: unexpected IO-APIC, please mail
kernel: to linux-smp@vger.kernel.org
Below are what I think are the relevant/helpful entries from dmesg from
the boot sequence. If anyone would like more information about the system
our would like me to run some commands to provide more diagnostic
information, I'd be happy to.
Thanks!!
Brian
dmesg line near initializing the CPUs:
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Hyper-Threading is disabled
Intel machine check architecture supported.
Intel machine check reporting enabled on CPU#0.
CPU: After generic, caps: bfebfbff 00000000 00000000 00000000
CPU: Common caps: bfebfbff 00000000 00000000 00000000
Enabling fast FPU save and restore... done.
Enabling unmasked SIMD FPU exception support... done.
Checking 'hlt' instruction... OK.
POSIX conformance testing by UNIFIX
mtrr: v1.40 (20010327) Richard Gooch (rgooch@atnf.csiro.au)
mtrr: detected mtrr type: Intel
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Hyper-Threading is disabled
Intel machine check reporting enabled on CPU#0.
CPU: After generic, caps: bfebfbff 00000000 00000000 00000000
CPU: Common caps: bfebfbff 00000000 00000000 00000000
CPU0: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07
per-CPU timeslice cutoff: 1462.38 usecs.
enabled ExtINT on CPU#0
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Booting processor 1/6 eip 2000
Initializing CPU#1
masked ExtINT on CPU#1
ESR value before enabling vector: 00000000
ESR value after enabling vector: 00000000
Calibrating delay loop... 4797.23 BogoMIPS
CPU: Trace cache: 12K uops, L1 D cache: 8K
CPU: L2 cache: 512K
CPU: Hyper-Threading is disabled
Intel machine check reporting enabled on CPU#1.
CPU: After generic, caps: bfebfbff 00000000 00000000 00000000
CPU: Common caps: bfebfbff 00000000 00000000 00000000
CPU1: Intel(R) Xeon(TM) CPU 2.40GHz stepping 07
Total of 2 processors activated (9581.36 BogoMIPS).
ENABLING IO-APIC IRQs
Setting 4 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 4 ... ok.
Setting 5 in the phys_id_present_map
...changing IO-APIC physical APIC ID to 5 ... ok.
BIOS bug, IO-APIC#2 ID 6 is already used!...
... fixing up to 1. (tell your hw vendor)
...changing IO-APIC physical APIC ID to 1 ... ok.
init IO_APIC IRQs
IO-APIC (apicid-pin) 4-0, 4-5, 4-9, 4-10, 4-11, 4-18, 4-20, 4-22, 5-0,
5-1, 5-2, 5-3, 5-4, 5-5, 5-6, 5-7, 5-10, 5-11, 5-12, 5-13, 5-14, 5-15,
5-16, 5-17, 5-18, 5-19, 5-20, 5-21, 5-22, 5-23, 1-1, 1-2, 1-3, 1-4, 1-5,
1-6, 1-7, 1-8, 1-9, 1-10, 1-11, 1-12, 1-13, 1-14, 1-15, 1-16, 1-17, 1-18,
1-19, 1-20, 1-21, 1-22, 1-23 not connected.
..TIMER: vector=0x31 pin1=2 pin2=0
number of MP IRQ sources: 23.
number of IO-APIC #4 registers: 24.
number of IO-APIC #5 registers: 24.
number of IO-APIC #1 registers: 24.
testing the IO APIC.......................
IO APIC #4......
.... register #00: 04000000
....... : physical APIC id: 04
.... register #01: 00178020
....... : max redirection entries: 0017
....... : PRQ implemented: 1
....... : IO APIC version: 0020
.... register #02: 00000000
....... : arbitration: 00
.... IRQ redirection table:
NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:
00 000 00 1 0 0 0 0 0 0 00
01 0FF 0F 0 0 0 0 0 1 1 39
02 0FF 0F 0 0 0 0 0 1 1 31
03 0FF 0F 0 0 0 0 0 1 1 41
04 0FF 0F 0 0 0 0 0 1 1 49
05 000 00 1 0 0 0 0 0 0 00
06 0FF 0F 0 0 0 0 0 1 1 51
07 0FF 0F 0 0 0 0 0 1 1 59
08 0FF 0F 0 0 0 0 0 1 1 61
09 000 00 1 0 0 0 0 0 0 00
0a 000 00 1 0 0 0 0 0 0 00
0b 000 00 1 0 0 0 0 0 0 00
0c 0FF 0F 0 0 0 0 0 1 1 69
0d 0FF 0F 0 0 0 0 0 1 1 71
0e 0FF 0F 0 0 0 0 0 1 1 79
0f 0FF 0F 0 0 0 0 0 1 1 81
10 0FF 0F 1 1 0 1 0 1 1 89
11 0FF 0F 1 1 0 1 0 1 1 91
12 000 00 1 0 0 0 0 0 0 00
13 0FF 0F 1 1 0 1 0 1 1 99
14 000 00 1 0 0 0 0 0 0 00
15 0FF 0F 1 1 0 1 0 1 1 A1
16 000 00 1 0 0 0 0 0 0 00
17 0FF 0F 1 1 0 1 0 1 1 A9
IO APIC #5......
.... register #00: 05000000
....... : physical APIC id: 05
.... register #01: 00178020
....... : max redirection entries: 0017....... : PRQ implemented:
1
....... : IO APIC version: 0020
.... register #02: 05000000
....... : arbitration: 05
.... IRQ redirection table:
NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:
00 000 00 1 0 0 0 0 0 0 00
01 000 00 1 0 0 0 0 0 0 00
02 000 00 1 0 0 0 0 0 0 00
03 000 00 1 0 0 0 0 0 0 00
04 000 00 1 0 0 0 0 0 0 00
05 000 00 1 0 0 0 0 0 0 00
06 000 00 1 0 0 0 0 0 0 00
07 000 00 1 0 0 0 0 0 0 00
08 0FF 0F 1 1 0 1 0 1 1 B1
09 0FF 0F 1 1 0 1 0 1 1 B9
0a 000 00 1 0 0 0 0 0 0 00
0b 000 00 1 0 0 0 0 0 0 00
0c 000 00 1 0 0 0 0 0 0 00
0d 000 00 1 0 0 0 0 0 0 00
0e 000 00 1 0 0 0 0 0 0 00
0f 000 00 1 0 0 0 0 0 0 00
10 000 00 1 0 0 0 0 0 0 00
11 000 00 1 0 0 0 0 0 0 00
12 000 00 1 0 0 0 0 0 0 00
13 000 00 1 0 0 0 0 0 0 00
14 000 00 1 0 0 0 0 0 0 00
15 000 00 1 0 0 0 0 0 0 00
16 000 00 1 0 0 0 0 0 0 00
17 000 00 1 0 0 0 0 0 0 00
IO APIC #1......
.... register #00: 01000000
....... : physical APIC id: 01
.... register #01: 00178020
....... : max redirection entries: 0017
....... : PRQ implemented: 1
....... : IO APIC version: 0020
.... register #02: 01000000
....... : arbitration: 01
.... IRQ redirection table:
NR Log Phy Mask Trig IRR Pol Stat Dest Deli Vect:
00 0FF 0F 1 1 0 1 0 1 1 C1
01 000 00 1 0 0 0 0 0 0 00
02 000 00 1 0 0 0 0 0 0 00
03 000 00 1 0 0 0 0 0 0 00
04 000 00 1 0 0 0 0 0 0 00
05 000 00 1 0 0 0 0 0 0 00
06 000 00 1 0 0 0 0 0 0 00
07 000 00 1 0 0 0 0 0 0 00
08 000 00 1 0 0 0 0 0 0 00
09 000 00 1 0 0 0 0 0 0 00
0a 000 00 1 0 0 0 0 0 0 00
0b 000 00 1 0 0 0 0 0 0 00
0c 000 00 1 0 0 0 0 0 0 00
0d 000 00 1 0 0 0 0 0 0 00
0e 000 00 1 0 0 0 0 0 0 00
0f 000 00 1 0 0 0 0 0 0 00
10 000 00 1 0 0 0 0 0 0 00
11 000 00 1 0 0 0 0 0 0 00
12 000 00 1 0 0 0 0 0 0 00
13 000 00 1 0 0 0 0 0 0 00
14 000 00 1 0 0 0 0 0 0 00
15 000 00 1 0 0 0 0 0 0 00
16 000 00 1 0 0 0 0 0 0 00
17 000 00 1 0 0 0 0 0 0 00
IRQ to pin mappings:
IRQ0 -> 0:2
IRQ1 -> 0:1
IRQ3 -> 0:3
IRQ4 -> 0:4
IRQ6 -> 0:6
IRQ7 -> 0:7
IRQ8 -> 0:8
IRQ12 -> 0:12
IRQ13 -> 0:13
IRQ14 -> 0:14
IRQ15 -> 0:15
IRQ16 -> 0:16
IRQ17 -> 0:17
IRQ19 -> 0:19
IRQ21 -> 0:21
IRQ23 -> 0:23
IRQ32 -> 1:8
IRQ33 -> 1:9
IRQ48 -> 2:0
.................................... done.
Using local APIC timer interrupts.
calibrating APIC timer ...
..... CPU clock speed is 2400.1653 MHz.
..... host bus clock speed is 133.3422 MHz.
cpu: 0, clocks: 1333422, slice: 444474
CPU0<T0:1333408,T1:888928,D:6,S:444474,C:1333422>
cpu: 1, clocks: 1333422, slice: 444474
CPU1<T0:1333408,T1:444448,D:12,S:444474,C:1333422>
checking TSC synchronization across CPUs: passed.
Waiting on wait_init_idle (map = 0x2)
All processors have done init_idle
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