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List:       linux-scsi
Subject:    Re: Sync SCSI timing options
From:       Gérard_Roudier <groudier () free ! fr>
Date:       2001-09-22 8:17:35
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On Thu, 20 Sep 2001, Kaelin Colclasure wrote:

> I believe I am slowly getting a handle on how synchronous SCSI transfers
> may be implemented with the LSI53C1010, but I find one particular set of
> options completely opaque. Namely, the SCNTL4_XCLK[HS]_[DS]T bits. The
> description of, for example, SCNTL4_XCLKH_DT, reads:
>
> ``Extra clock of data hold on the DT transfer edge. Setting this bit
> adds a clock of data hold to synchronous DT SCSI transfers on the DT
> edge...''
>
> This explanation goes on to provide a timing diagram which shows the DT
> transfer cycle being distorted by the extra clock cycle. Now, why would
> anyone ever need/want to do this?

I don't want. Do you ? :)

> Wouldn't this put the adaptor out of
> spec, and likely cause timing problems with synchronous transfers?
> Usually bits that exist only for testing and diagnostic purposes are
> explicitly documented as such...

You are not required to use all possible combinations of these bits.
The 3 following combinations make all cycles in DT mode to be the same
width:

1) XCLKH_ST, XCLKH_DT, XCLKS_ST, XCLKS_DT all cleared.
2) Only XCLKH_ST and XCLKH_DT set.
3) Only XCLKS_ST and XCLKS_DT set.

By the way, the sym* drivers never tried to use any other combination of
these bits. :)

Regards,
  Gérard.

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