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List:       linux-omap
Subject:    [PATCH] Experimental DMA support for 24xx MMC
From:       tony () atomide ! com (Tony Lindgren)
Date:       2005-10-31 18:38:56
Message-ID: 20051101003842.GH16511 () atomide ! com
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Hi all,

Here's an ugly test patch for 24xx DMA using MMC. 

I'm getting occasional cache failures with this patch, so corruption
might happen :)

I'll look into the cache failures more during this week.

Regards,

Tony
-------------- next part --------------
diff --git a/drivers/mmc/omap.c b/drivers/mmc/omap.c
index 7b39a45..03c376d 100644
Index: linux-omap-dev/drivers/mmc/omap.c
===================================================================
--- linux-omap-dev.orig/drivers/mmc/omap.c	2005-10-28 10:14:03.000000000 -0700
+++ linux-omap-dev/drivers/mmc/omap.c	2005-10-31 16:08:13.000000000 -0800
@@ -677,9 +677,9 @@
 	u16 buf, frame;
 	u32 count;
 	struct scatterlist *sg = &data->sg[host->sg_idx];
+	int sync_dev = 0;
 
-	data_addr = virt_to_phys((void __force *) host->base)
-				+ OMAP_MMC_REG_DATA;
+	data_addr = io_v2p((void __force *) host->base) + OMAP_MMC_REG_DATA;
 	frame = 1 << data->blksz_bits;
 	count = sg_dma_len(sg);
 
@@ -702,28 +702,68 @@
 
 	if (!(data->flags & MMC_DATA_WRITE)) {
 		buf = 0x800f | ((frame - 1) << 8);
-		omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_TIPB,
-					OMAP_DMA_AMODE_CONSTANT,
-					data_addr,
-					0, 0);
-		omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_EMIFF,
-					OMAP_DMA_AMODE_POST_INC,
-					sg_dma_address(sg),
-					0, 0);
-		omap_set_dma_dest_data_pack(dma_ch, 1);
-		omap_set_dma_dest_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
+
+		if (cpu_class_is_omap1()) {
+			omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_TIPB,
+						OMAP_DMA_AMODE_CONSTANT,
+						data_addr,
+						0, 0);
+			omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_EMIFF,
+						 OMAP_DMA_AMODE_POST_INC,
+						 sg_dma_address(sg),
+						 0, 0);
+			omap_set_dma_dest_data_pack(dma_ch, 1);
+			omap_set_dma_dest_burst_mode(dma_ch,
+						     OMAP_DMA_DATA_BURST_4);
+		}
+
+		if (cpu_is_omap24xx()) {
+			sync_dev = OMAP24XX_DMA_MMC1_RX;
+			omap_set_dma_src_params(dma_ch, 0,
+						OMAP_DMA_AMODE_CONSTANT,
+						data_addr,
+						0, 0);
+			omap_set_dma_dest_params(dma_ch, 0,
+						 OMAP_DMA_AMODE_POST_INC,
+						 sg_dma_address(sg),
+						 0, 0);
+			omap_set_dma_dest_data_pack(dma_ch, 1);
+			omap_set_dma_dest_burst_mode(dma_ch,
+						     OMAP_DMA_DATA_BURST_4);
+		}
+
 	} else {
 		buf = 0x0f80 | ((frame - 1) << 0);
-		omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_TIPB,
-					OMAP_DMA_AMODE_CONSTANT,
-					data_addr,
-					0, 0);
-		omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_EMIFF,
-					OMAP_DMA_AMODE_POST_INC,
-					sg_dma_address(sg),
-					0, 0);
-		omap_set_dma_src_data_pack(dma_ch, 1);
-		omap_set_dma_src_burst_mode(dma_ch, OMAP_DMA_DATA_BURST_4);
+
+		if (cpu_class_is_omap1()) {
+			omap_set_dma_dest_params(dma_ch, OMAP_DMA_PORT_TIPB,
+						 OMAP_DMA_AMODE_CONSTANT,
+						 data_addr,
+						 0, 0);
+			omap_set_dma_src_params(dma_ch, OMAP_DMA_PORT_EMIFF,
+						OMAP_DMA_AMODE_POST_INC,
+						sg_dma_address(sg),
+						0, 0);
+			omap_set_dma_src_data_pack(dma_ch, 1);
+			omap_set_dma_src_burst_mode(dma_ch,
+						    OMAP_DMA_DATA_BURST_4);
+		}
+
+		if (cpu_is_omap24xx()) {
+			sync_dev = OMAP24XX_DMA_MMC1_TX;
+			omap_set_dma_dest_params(dma_ch, 0,
+						 OMAP_DMA_AMODE_CONSTANT,
+						 data_addr,
+						 0, 0);
+			omap_set_dma_src_params(dma_ch, 0,
+						OMAP_DMA_AMODE_POST_INC,
+						sg_dma_address(sg),
+						0, 0);
+			omap_set_dma_src_data_pack(dma_ch, 1);
+			omap_set_dma_src_burst_mode(dma_ch,
+						    OMAP_DMA_DATA_BURST_4);
+
+		}
 	}
 
 	/* Max limit for DMA frame count is 0xffff */
@@ -731,9 +771,10 @@
 		BUG();
 
 	OMAP_MMC_WRITE(host->base, BUF, buf);
+
 	omap_set_dma_transfer_params(dma_ch, OMAP_DMA_DATA_TYPE_S16,
-			frame, count, OMAP_DMA_SYNC_FRAME,
-			0, 0);
+				     frame, count, OMAP_DMA_SYNC_FRAME,
+				     sync_dev, 0);
 }
 
 /* a scatterlist segment completed */
@@ -763,7 +804,15 @@
 		if ((ch_status & ~OMAP_DMA_SYNC_IRQ))
 			pr_debug("MMC%d: DMA channel status: %04x\n",
 			       host->id, ch_status);
-		return;
+
+		/*
+		 * REVISIT: On omap1 the status should be 0x20, on 2420
+		 * it can be 0x00
+		 */
+#if 0
+		if (cpu_class_is_omap1())
+			return;
+#endif
 	}
 	mmcdat->bytes_xfered += host->dma_len;
 
@@ -1211,12 +1260,7 @@
 	host->power_pin = minfo->power_pin;
 	host->switch_pin = minfo->switch_pin;
 	host->wp_pin = minfo->wp_pin;
-
-	/* FIXME: Remove once DMA works on 24xx */
-	if (cpu_is_omap24xx())
-		host->use_dma = 0;
-	else
-		host->use_dma = 1;
+	host->use_dma = 1;
 	host->dma_ch = -1;
 
 	host->irq = pdev->resource[1].start;

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