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List:       linux-mips-cvs
Subject:    MIPS: c-r4k.c: Fix the 74K D-cache alias erratum workaround
From:       linux-mips () linux-mips ! org
Date:       2015-04-12 19:27:02
Message-ID: S27014518AbbDLT1Faf94t/20150412192705Z+208 () eddie ! linux-mips ! org
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Author: Maciej W. Rozycki <macro@codesourcery.com> Sun Nov 16 01:02:29 2014 +0000
Comitter: Ralf Baechle <ralf@linux-mips.org> Tue Mar 31 22:55:40 2015 +0200
Commit: 61a89e39eaa6737c2807d1118ffca593b7dcd7b1
Gitweb: http://git.linux-mips.org/g/ralf/linux/61a89e39eaa6
Branch: linux-3.19-stable

Fix the 74K D-cache alias erratum workaround so that it actually works.
Our current code sets MIPS_CACHE_VTAG for the D-cache, but that flag
only has any effect for the I-cache.  Additionally MIPS_CACHE_PINDEX is
set for the D-cache if CP0.Config7.AR is also set for an affected
processor, leading to confusing information in the bootstrap log (the
flag isn't used beyond that).

So delete the setting of MIPS_CACHE_VTAG and rely on MIPS_CACHE_ALIASES,
set in a common place, removing I-cache coherency issues seen in GDB
testing with software breakpoints, gdbserver and ptrace(2), on affected
systems.

While at it add a little piece of explanation of what CP0.Config6.SYND
is so that people do not have to chase documentation.

Signed-off-by: Maciej W. Rozycki <macro@codesourcery.com>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8507/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit f289cd2af3c6a71e4b05e8a9ae8a9c23708c6553)

---

 arch/mips/mm/c-r4k.c |   23 +++++++++++++++--------
 1 file changed, 15 insertions(+), 8 deletions(-)

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