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List:       linux-mips-cvs
Subject:    MIPS: Fix C0_Pagegrain[IEC] support.
From:       linux-mips () linux-mips ! org
Date:       2015-01-30 23:38:14
Message-ID: S27012349AbbA3XiRXHuC7/20150130233817Z+536 () eddie ! linux-mips ! org
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Author: David Daney <david.daney@cavium.com> Tue Jan 6 10:42:23 2015 -0800
Comitter: Ralf Baechle <ralf@linux-mips.org> Fri Jan 30 23:24:21 2015 +0100
Commit: aa54f4fb2d730c5e9b99cb9e2ac662f1c0d75fdb
Gitweb: http://git.linux-mips.org/g/ralf/linux/aa54f4fb2d73
Branch: linux-3.17-stable

The following commits:

  5890f70f15c52d (MIPS: Use dedicated exception handler if CPU supports RI/XI exceptions)
  6575b1d4173eae (MIPS: kernel: cpu-probe: Detect unique RI/XI exceptions)

break the kernel for *all* existing MIPS CPUs that implement the
CP0_PageGrain[IEC] bit.  They cause the TLB exception handlers to be
generated without the legacy execute-inhibit handling, but never set
the CP0_PageGrain[IEC] bit to activate the use of dedicated exception
vectors for execute-inhibit exceptions.  The result is that upon
detection of an execute-inhibit violation, we loop forever in the TLB
exception handlers instead of sending SIGSEGV to the task.

If we are generating TLB exception handlers expecting separate
vectors, we must also enable the CP0_PageGrain[IEC] feature.

The bug was introduced in kernel version 3.17.

Signed-off-by: David Daney <david.daney@cavium.com>
Cc: <stable@vger.kernel.org>
Cc: Leonid Yegoshin <Leonid.Yegoshin@imgtec.com>
Cc: linux-mips@linux-mips.org
Patchwork: http://patchwork.linux-mips.org/patch/8880/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit 4caaf26cad00604b6f5a60dc376c1e73134c534a)

---

 arch/mips/mm/tlb-r4k.c |    2 ++
 1 file changed, 2 insertions(+)

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