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List:       linux-mips-cvs
Subject:    MIPS: Do not fiddle with FRE unless FRE is actually available.
From:       linux-mips () linux-mips ! org
Date:       2014-12-17 11:42:58
Message-ID: S27008527AbaLQLnA5Bvi7/20141217114301Z+2921 () eddie ! linux-mips ! org
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Author: Ralf Baechle <ralf@linux-mips.org> Wed Dec 17 11:39:30 2014 +0100
Commit: aa00b564f7c29fd2335f1527a1862dedd339dcfa
Gitweb: http://git.linux-mips.org/g/ralf/linux/aa00b564f7c2
Branch: master

Commit 4227a2d4efc9c84f35826dc4d1e6dc183f6c1c05 (MIPS: Support for hybrid
FPRs) changes the kernel to execute read_c0_config5() even on processors
that don't have a Config5 register.  According to the arch spec the
behaviour of trying to read or write this register is UNDEFINED where this
register doesn't exist, that is merely looking at this register is
already cruel because that might kill a kitten.

In case of Qemu older than v2.2 Qemu has elected to implement this
UNDEFINED behaviour by taking a RI exception - which then fries the
kernel:

[...]
Freeing YAMON memory: 956k freed
Freeing unused kernel memory: 240K (80674000 - 806b0000)
Reserved instruction in kernel code[#1]:
CPU: 0 PID: 1 Comm: init Not tainted 3.18.0-rc6-00058-g4227a2d #26
task: 86047588 ti: 86048000 task.ti: 86048000
$ 0   : 00000000 77a638cc 00000000 00000000
[...]

For qemu v2.2.0 commit f31b035a9f10dc9b57f01c426110af845d453ce2
(target-mips: correctly handle access to unimplemented CP0 register)
changed the behaviour to returning zero on read and ignoring writes
which more matches how typical hardware implementations actually behave.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---

 arch/mips/include/asm/fpu.h |   43 +++++++++++++++++++++++++++----------------
 1 file changed, 27 insertions(+), 16 deletions(-)

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