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List:       linux-mips-cvs
Subject:    MIPS: Fix ISA level which causes secondary cache init bypassing and more
From:       linux-mips () linux-mips ! org
Date:       2013-04-08 13:30:36
Message-ID: S6827533Ab3DHNaqrmHHP/20130408133046Z+1693 () eddie ! linux-mips ! org
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Author: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com> Mon Apr 1 18:14:28 2013 +0000
Comitter: Ralf Baechle <ralf@linux-mips.org> Fri Apr 5 14:42:09 2013 +0200
Commit: 4b2e526ebfdbed8e99bfb2dfcb2a3a425b7ae538
Gitweb: http://git.linux-mips.org/g/ralf/linux/4b2e526ebfdb
Branch: master

The commit a96102be70 introduced set_isa() where compatible ISA info is
also set aside from the one gets passed in. It means, for example, 1004K
will have MIPS_CPU_ISA_M32R2/M32R1/II/I flags. This leads to things like
the following inappropriate:

if (c->isa_level == MIPS_CPU_ISA_M32R1 ||
    c->isa_level == MIPS_CPU_ISA_M32R2 ||
    c->isa_level == MIPS_CPU_ISA_M64R1 ||
    c->isa_level == MIPS_CPU_ISA_M64R2)

This patch fixes it.

Signed-off-by: Deng-Cheng Zhu <dengcheng.zhu@imgtec.com>
Cc: Steven J. Hill <Steven.Hill@imgtec.com>
Cc: linux-mips@linux-mips.org
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---

 arch/mips/kernel/cpu-probe.c |    6 ++----
 arch/mips/kernel/traps.c     |    2 +-
 arch/mips/mm/c-r4k.c         |    6 ++----
 arch/mips/mm/sc-mips.c       |    6 ++----
 4 files changed, 7 insertions(+), 13 deletions(-)

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