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List:       linux-mips-cvs
Subject:    MIPS: Sibyte: Apply M3 workaround only on affected chip types and versions.
From:       linux-mips () linux-mips ! org
Date:       2010-03-24 17:38:58
Message-ID: S1492890Ab0CXRjC/20100324173902Z+2223 () eddie ! linux-mips ! org
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Author: Ralf Baechle <ralf@linux-mips.org> Tue Mar 23 00:02:43 2010 +0100
Commit: ed33205d2bd0118b50e2a86440135e935c35ea56
Gitweb: http://www.linux-mips.org/g/linux/ed33205d
Branch: linux-2.6.31-stable

Previously it was unconditionally used on all Sibyte family SOCs.  The
M3 bug has to be handled in the TLB exception handler which is extremly
performance sensitive, so this modification is expected to deliver around
2-3% performance improvment.  This is important as required changes to the
M3 workaround will make it more costly.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
(cherry picked from commit e65c7f33d75e977350ca350573d93c517ec02776)

---

 arch/mips/include/asm/mach-sibyte/war.h |    6 +++++-
 arch/mips/sibyte/sb1250/setup.c         |   15 +++++++++++++++
 2 files changed, 20 insertions(+), 1 deletions(-)

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