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List:       linux-mips
Subject:    Re: [PATCH 1/1] MIPS: math-emu: cp1emu: Fix typo when returning to register file
From:       Aurelien Jarno <aurelien () aurel32 ! net>
Date:       2014-07-30 16:53:00
Message-ID: 20140730165300.GB4848 () ohm ! rr44 ! fr
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On Wed, Jul 23, 2014 at 01:41:58PM +0100, Rob Kendrick wrote:
> The commit 08a07904e182895e1205f399465a3d622c0115b8 (v3.16-rc1)
> entitled "MIPS: math-emu: Remove most ifdefery":
> 
> switched from build time to runtime detection for the CPU ISA level.
> 
> However, along the way, a typo was introduced in the code path
> to return the value to the register file. Previously, the
> MIPSInst_FD macro was used but the above commit switched to
> MIPSInst_RT leading to regressions.
> 
> Link: http://www.linux-mips.org/archives/linux-mips/2014-07/msg00484.html
> Reported-by: Rob Kendrick <rob.kendrick@codethink.co.uk>
> Reviewed-by: Paul Burton <paul.burton@imgtec.com>
> Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
> Signed-off-by: Rob Kendrick <rob.kendrick@codethink.co.uk>
> ---
>  arch/mips/math-emu/cp1emu.c |    2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/arch/mips/math-emu/cp1emu.c b/arch/mips/math-emu/cp1emu.c
> index 736c17a..bf0fc6b 100644
> --- a/arch/mips/math-emu/cp1emu.c
> +++ b/arch/mips/math-emu/cp1emu.c
> @@ -1827,7 +1827,7 @@ dcopuop:
>  	case -1:
>  
>  		if (cpu_has_mips_4_5_r)
> -			cbit = fpucondbit[MIPSInst_RT(ir) >> 2];
> +			cbit = fpucondbit[MIPSInst_FD(ir) >> 2];
>  		else
>  			cbit = FPU_CSR_COND;
>  		if (rv.w)

Looking at commit 8a07904e, the typo looks obvious. Moreover I have
tested that using QEMU, and I can confirm the issue. I can also confirm
the patch fixes the issue.

Tested-by: Aurelien Jarno <aurelien@aurel32.net>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

-- 
Aurelien Jarno                          GPG: 4096R/1DDD8C9B
aurelien@aurel32.net                 http://www.aurel32.net

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