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List:       linux-mips
Subject:    Re: [PATCH][MIPS] Use CP0 Count register to implement more granular
From:       David VomLehn <dvomlehn () cisco ! com>
Date:       2009-03-25 17:37:49
Message-ID: 49CA6BED.60505 () cisco ! com
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Mauricio Culibrk wrote:
> Hi there!
> 
> I'm really sorry for bothering you.... I noticed your posts and patch on 
> the linux-mips mailing list....
> and I'm very interested in ndelay patch you proposed.
> 
> I'm currently using some embedded mips-based boards for bit-banging SPI 
> and I2C implementations... but the current code uses udelay which is way 
> too "long" for the purporse...
> 
> I'm wondering if you have any updated/fixed patch available as you 
> mention that on the list (that you'll fix your patch a little regarding 
> all the comments received)
> 
> Anyway... I'm using some "consumer" boards based on Atheros WiSoCs 
> AR2315, AR2317... and Broadcom chips which should have MIPS32 MIPS4K 
> cores...
> this cpu should have a "functioning cr0 register", right? (as I have 
> absolutely no "datasheets" available to check for that)

The latest version of the ndelay patch is version 3, which disables 
interrupts to ensure the Count register doesn't wrap. If you have 
interrupts disabled already, there is another function you can can call. 
You can get the version 3 patch from the mailing list archive at 
http://www.linux-mips.org/archives/linux-mips/2009-03/msg00073.html

I haven't received much feedback since the first version of the patch, 
and it's something we're already using, so I think it's in pretty good 
shape. And, as I understand it, R4000-series processors should be in 
shape as far as a good Count register. Part of the version 3 patch adds 
dependencies so that it will only appear in your favorite configuration 
tool if you've selected a processor on which it will work. Ralf has 
mentioned some issues with some R4000 processors, though.

As the code stands on my 24K processor, a requested delay of 100 nsec 
ends up as an actual delay of a bit over 130 nsec. Not perfect, but 
definitely less than 1000 nsec. I have been thinking about adding in a 
calibration constant that should get it closer, but it hasn't been 
important yet and I wanted the basic patch to get accepted before I did 
anything *really* obscure.

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