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List:       linux-gpio
Subject:    Re: [v2, 0/2] Fix broken SET/CLR mode of a certain number of pins for MediaTek MT8385 SoC
From:       Kevin Hilman <khilman () kernel ! org>
Date:       2022-10-31 16:40:04
Message-ID: 7h5yg02bh7.fsf () baylibre ! com
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Hi Balsam,


bchihi@baylibre.com writes:

> From: Balsam CHIHI <bchihi@baylibre.com>
> 
> On MT8365, the SET/CLR of the mode is broken and some pins won't set or clear the \
> modes correctly. To fix this issue, we add a specific callback \
> mt8365_set_clr_mode() for this specific SoC. This callback uses the main R/W \
> register to read/update/write the modes instead of using the SET/CLR register. 
> This is the original patch series proposed by Fabien Parent <fparent@baylibre.com>.
> "https://lore.kernel.org/linux-arm-kernel/20220530123425.689459-1-fparent@baylibre.com/"
>  
> Changelog:
> Changes in v2 :
> - Rebase on top of 6.1.0-rc1-next-20221020
> - Delete MTK_PINCTRL_MODE_SET_CLR_BROKEN quirk
> - Add mt8365_set_clr_mode() callback

nit: subject of cover letter should also include "pinctrl: mediatek:"
prefix.  Also note that you're missing the word "PATCH" in all of the
subjects.

Tip: If you use `git format-patch`, you can just pass `-v2` on the
cmdline and it will create the prefixes for you automatically.

Kevin


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