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List:       linux-fpga
Subject:    Re: [PATCH v6 1/5] fpga: zynq: Fix incorrect variable type
From:       Xu Yilun <yilun.xu () intel ! com>
Date:       2022-04-25 13:23:46
Message-ID: 20220425132346.GB367066 () yilunxu-OptiPlex-7050
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On Sat, Apr 23, 2022 at 10:32:31PM +0530, Nava kishore Manne wrote:
> zynq_fpga_has_sync () API is expecting "u8 *" but the
> formal parameter that was passed is of type "const char *".
> fix this issue by changing the buf type to "const char *"
> 
> Signed-off-by: Nava kishore Manne <nava.manne@xilinx.com>
> Acked-by: Xu Yilun <yilun.xu@intel.com>

Hi Nava:

There is a lkp bug report yet to be fixed. Please fix it.

Thanks,
Yilun

> ---
> Changes for v2:
>                 -None.
> Changes for v3:
>                - Changed arg buf type to "const char *" as suggested by Tom.
>                - update zynq_fpga_has_sync () API description to align with API
>                  functionality.
> Changes for v4:
>                - None.
> 
> Changes for v5:
>                - Dropped the irrelevant doc update changes.
> Changes for v6:
>                - None.
> 
>  drivers/fpga/zynq-fpga.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/fpga/zynq-fpga.c b/drivers/fpga/zynq-fpga.c
> index 426aa34c6a0d..6beaba9dfe97 100644
> --- a/drivers/fpga/zynq-fpga.c
> +++ b/drivers/fpga/zynq-fpga.c
> @@ -239,7 +239,7 @@ static irqreturn_t zynq_fpga_isr(int irq, void *data)
>   * the correct byte order, and be dword aligned. The input is a Xilinx .bin
>   * file with every 32 bit quantity swapped.
>   */
> -static bool zynq_fpga_has_sync(const u8 *buf, size_t count)
> +static bool zynq_fpga_has_sync(const char *buf, size_t count)
>  {
>  	for (; count >= 4; buf += 4, count -= 4)
>  		if (buf[0] == 0x66 && buf[1] == 0x55 && buf[2] == 0x99 &&
> -- 
> 2.25.1
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