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List:       linux-ecc
Subject:    RE: [ecc] Re: Status on ServerWorks chipsets?
From:       Jonathan Lundell <jlundell () pobox ! com>
Date:       2003-03-14 22:08:09
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At 4:53pm -0500 3/14/03, Dana Lacoste wrote:
>Whatever happens, I have an IBM x335 or two I can test with.
>
>Unfortunately, I have to do windows install development this
>month (d'oh!) so i can't offer much in the way of coding, but
>I can run tests if you throw them at me :)

That'd be interesting. I'd frankly be amazed if the current code 
supports Grand Champion, but I suppose stranger things have happened. 
I don't suppose anybody on the list has GC docs....

The first test is to see if the chipset gets recognized, and then 
whether it reports your memory configuration properly. If there are 
problems, an lspci -vxxx of the bridge device(s) might help.

This kind of thing is pretty hard to reverse engineer from lspci 
output. A case in point is the E7500. The ecc error regs are in 
device 0 function 1 (d0f1), but there was no d0f1 in lspci on my Tyan 
box. A little probing showed that there was no d0f1 in configuration 
space.

Fortunately Intel publishes its docs. It turns out that there's a bit 
in a register in d0f0 that hides d0f1. Why would you want to do that? 
I dunno, but there you are. Turning that bit off makes d0f1 appear in 
config space, but of course it's not in the kernel's device list. So 
we have to fake a struct pci_dev for d0f1 in order to be able to use 
the config-space routines to look at the ecc error regs.

Well, that's a little long-winded, but you can see it would have been 
impossible to figure out without the docs.
-- 
/Jonathan Lundell.

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