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List:       linux-clk
Subject:    Re: [PATCH v1 2/4] clk: qcom: Add support for Display Clock Controller on SM8450
From:       Rob Herring <robh () kernel ! org>
Date:       2022-06-30 21:52:47
Message-ID: 20220630215247.GA3375216-robh () kernel ! org
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On Thu, Jun 23, 2022 at 02:47:35PM +0300, Dmitry Baryshkov wrote:
> Add support for the dispcc on Qualcomm SM8450 platform.
> 
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
> ---
> drivers/clk/qcom/Kconfig                      |    9 +
> drivers/clk/qcom/Makefile                     |    1 +
> drivers/clk/qcom/dispcc-sm8450.c              | 1806 +++++++++++++++++
> .../dt-bindings/clock/qcom,dispcc-sm8450.h    |  103 +

This belongs in binding patch.

> 4 files changed, 1919 insertions(+)
> create mode 100644 drivers/clk/qcom/dispcc-sm8450.c
> create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8450.h


> diff --git a/include/dt-bindings/clock/qcom,dispcc-sm8450.h \
> b/include/dt-bindings/clock/qcom,dispcc-sm8450.h new file mode 100644
> index 000000000000..653ce8d47fe6
> --- /dev/null
> +++ b/include/dt-bindings/clock/qcom,dispcc-sm8450.h
> @@ -0,0 +1,103 @@
> +/* SPDX-License-Identifier: GPL-2.0-only */

Dual license.

> +/*
> + * Copyright (c) 2020, The Linux Foundation. All rights reserved.

It's 2022.

> + */
> +
> +#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H
> +#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SM8450_H
> +
> +/* DISP_CC clocks */
> +#define DISP_CC_MDSS_AHB1_CLK					0
> +#define DISP_CC_MDSS_AHB_CLK					1
> +#define DISP_CC_MDSS_AHB_CLK_SRC				2
> +#define DISP_CC_MDSS_BYTE0_CLK					3
> +#define DISP_CC_MDSS_BYTE0_CLK_SRC				4
> +#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC				5
> +#define DISP_CC_MDSS_BYTE0_INTF_CLK				6
> +#define DISP_CC_MDSS_BYTE1_CLK					7
> +#define DISP_CC_MDSS_BYTE1_CLK_SRC				8
> +#define DISP_CC_MDSS_BYTE1_DIV_CLK_SRC				9
> +#define DISP_CC_MDSS_BYTE1_INTF_CLK				10
> +#define DISP_CC_MDSS_DPTX0_AUX_CLK				11
> +#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC				12
> +#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK				13
> +#define DISP_CC_MDSS_DPTX0_LINK_CLK				14
> +#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC				15
> +#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC			16
> +#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK			17
> +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK				18
> +#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC			19
> +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK				20
> +#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC			21
> +#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK		22
> +#define DISP_CC_MDSS_DPTX1_AUX_CLK				23
> +#define DISP_CC_MDSS_DPTX1_AUX_CLK_SRC				24
> +#define DISP_CC_MDSS_DPTX1_CRYPTO_CLK				25
> +#define DISP_CC_MDSS_DPTX1_LINK_CLK				26
> +#define DISP_CC_MDSS_DPTX1_LINK_CLK_SRC				27
> +#define DISP_CC_MDSS_DPTX1_LINK_DIV_CLK_SRC			28
> +#define DISP_CC_MDSS_DPTX1_LINK_INTF_CLK			29
> +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK				30
> +#define DISP_CC_MDSS_DPTX1_PIXEL0_CLK_SRC			31
> +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK				32
> +#define DISP_CC_MDSS_DPTX1_PIXEL1_CLK_SRC			33
> +#define DISP_CC_MDSS_DPTX1_USB_ROUTER_LINK_INTF_CLK		34
> +#define DISP_CC_MDSS_DPTX2_AUX_CLK				35
> +#define DISP_CC_MDSS_DPTX2_AUX_CLK_SRC				36
> +#define DISP_CC_MDSS_DPTX2_CRYPTO_CLK				37
> +#define DISP_CC_MDSS_DPTX2_LINK_CLK				38
> +#define DISP_CC_MDSS_DPTX2_LINK_CLK_SRC				39
> +#define DISP_CC_MDSS_DPTX2_LINK_DIV_CLK_SRC			40
> +#define DISP_CC_MDSS_DPTX2_LINK_INTF_CLK			41
> +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK				42
> +#define DISP_CC_MDSS_DPTX2_PIXEL0_CLK_SRC			43
> +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK				44
> +#define DISP_CC_MDSS_DPTX2_PIXEL1_CLK_SRC			45
> +#define DISP_CC_MDSS_DPTX3_AUX_CLK				46
> +#define DISP_CC_MDSS_DPTX3_AUX_CLK_SRC				47
> +#define DISP_CC_MDSS_DPTX3_CRYPTO_CLK				48
> +#define DISP_CC_MDSS_DPTX3_LINK_CLK				49
> +#define DISP_CC_MDSS_DPTX3_LINK_CLK_SRC				50
> +#define DISP_CC_MDSS_DPTX3_LINK_DIV_CLK_SRC			51
> +#define DISP_CC_MDSS_DPTX3_LINK_INTF_CLK			52
> +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK				53
> +#define DISP_CC_MDSS_DPTX3_PIXEL0_CLK_SRC			54
> +#define DISP_CC_MDSS_ESC0_CLK					55
> +#define DISP_CC_MDSS_ESC0_CLK_SRC				56
> +#define DISP_CC_MDSS_ESC1_CLK					57
> +#define DISP_CC_MDSS_ESC1_CLK_SRC				58
> +#define DISP_CC_MDSS_MDP1_CLK					59
> +#define DISP_CC_MDSS_MDP_CLK					60
> +#define DISP_CC_MDSS_MDP_CLK_SRC				61
> +#define DISP_CC_MDSS_MDP_LUT1_CLK				62
> +#define DISP_CC_MDSS_MDP_LUT_CLK				63
> +#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				64
> +#define DISP_CC_MDSS_PCLK0_CLK					65
> +#define DISP_CC_MDSS_PCLK0_CLK_SRC				66
> +#define DISP_CC_MDSS_PCLK1_CLK					67
> +#define DISP_CC_MDSS_PCLK1_CLK_SRC				68
> +#define DISP_CC_MDSS_ROT1_CLK					69
> +#define DISP_CC_MDSS_ROT_CLK					70
> +#define DISP_CC_MDSS_ROT_CLK_SRC				71
> +#define DISP_CC_MDSS_RSCC_AHB_CLK				72
> +#define DISP_CC_MDSS_RSCC_VSYNC_CLK				73
> +#define DISP_CC_MDSS_VSYNC1_CLK					74
> +#define DISP_CC_MDSS_VSYNC_CLK					75
> +#define DISP_CC_MDSS_VSYNC_CLK_SRC				76
> +#define DISP_CC_PLL0						77
> +#define DISP_CC_PLL1						78
> +#define DISP_CC_SLEEP_CLK					79
> +#define DISP_CC_SLEEP_CLK_SRC					80
> +#define DISP_CC_XO_CLK						81
> +#define DISP_CC_XO_CLK_SRC					82
> +
> +/* DISP_CC resets */
> +#define DISP_CC_MDSS_CORE_BCR					0
> +#define DISP_CC_MDSS_CORE_INT2_BCR				1
> +#define DISP_CC_MDSS_RSCC_BCR					2
> +
> +/* DISP_CC GDSCR */
> +#define MDSS_GDSC				0
> +#define MDSS_INT2_GDSC				1
> +
> +#endif
> -- 
> 2.35.1
> 
> 


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