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List:       linux-arm-kernel
Subject:    Re: Re: problem of modifying AT91RM9200's process or clock and
From:       Jeff Warren <tiny.laser () comcast ! net>
Date:       2007-01-30 17:46:08
Message-ID: 1170179168.9706.1.camel () TinyLinux
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On Tue, 2007-01-30 at 09:42, Jeff Warren wrote:
> On Tue, 2007-01-30 at 00:24, jonghne@163.com wrote:
> > I just want to change master clock(not change PLL or any other clocks) from 60MHz \
> > to 45MHz, so I modify PMC_MCKR in simple-boot. With this new boot, after it print \
> > strartup infomation, it died, I think it maybe died at the point where the boot \
> > was moving u-boot from flash to SDRAM. flash is intel 28f128j3c, SDRAM is \
> > K4S561632C-75, can't the 45MHz MCK support these memory? Is it possible that it's \
> > the problem for USART? how can I do? Best regards.
> > 
> > 
> > 
> > 
> > on 2007-01-29，"Andy Green" <andy@warmcat.com> wrote：
> > 
> > jonghne@163.com wrote:
> > 
> > > hi. I modified AT91RM9200's processor clock and master clock
> > > frequencies by re-write PMC's MCKR and PLLAR registers in my driver,
> > > after system ran, I insmod the driver, but the system died . why?
> > > can't I do this ? Best regards 
> > 
> > Well it seems you can do it, but it crashes your system ;-)  At least 
> > one of the clock registers in the AT91RM9200 has a constraint that if 
> > you write it, you must write *different* data.
> > 
> > Also, while the PLL is changing frequency I can imagine it can maybe 
> > generate illegally sized clock periods?  Try to change to the 32kHz 
> > clock for some time before changing PLLA and for some time afterwards too.
> > 
> If you change the MCKR and the PLLAR registers, you also have to change
> anything that gets its timing from the Master Clock, i.e. the RS232.  If
> I recall correctly, both u-boot and the kernel do NOT change those
> settings, but the baud rate is directly derived from the Master Clock. 
> Also there may be other things that will be affected.  
> In my experience though, the RAM always worked, regardless of the Master
> Clock divider.
> 
> Jeff Warren
Look for the DBGU_BRGR (baud rate generator) register in the code and
the description in the AT91RM9200 pdf.


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