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List:       linux-arm-kernel
Subject:    Re: PXA27x host port 2 non functional
From:       bernd.westermann () it-west ! de
Date:       2005-11-30 17:41:17
Message-ID: 200511301841.17057.bernd.westermann () it-west ! de
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Hi Nicola,

I found this solution too ( today, this mail was 6h to late :-( ).
But I think, do not put pxa_gpio_mode(...) in mainstone part of code, because 
they may use port 2 as device.

Bernd Westermann


Am Mittwoch, 30. November 2005 18:10 schrieb nicola perrino:
> Hi David,
>
> I solved this problem. It is necessary to set GAFR3_U to
> 0000-0000-0000-0010-01xx-xxxx-xxxx-xxxx ( I've set it in the bootloader)
> and to add:
>
> 	pxa_gpio_mode( 119 | GPIO_ALT_FN_1_IN);   /* USBHPWR2 */
> 	pxa_gpio_mode( 120 | GPIO_ALT_FN_2_OUT);  /* USBHPEN2 */
>
> in the pxa27x_start_hc() function.
>
> This is my solution:
>
> static void pxa27x_start_hc(struct platform_device *dev)
> {
> 	pxa_set_cken(CKEN10_USBHOST, 1);
>
> #ifdef CONFIG_MACH_MYBOARD
> 	/* Init USB Port 2 Output Control Register */
> 	UP2OCR = 0x00;
>
> 	/* Host Port 2 Transceiver Output Enable */
> 	UP2OCR |= UP2OCR_HXS;
> 	UP2OCR |= UP2OCR_HXOE;
>
> 	/* D+ Pull Up SW1 ON */
> 	UP2OCR |= (UP2OCR_DPPDE|UP2OCR_DMPDE);
> #endif
>
> 	UHCHR |= UHCHR_FHR;
> 	udelay(11);
> 	UHCHR &= ~UHCHR_FHR;
>
> 	UHCHR |= UHCHR_FSBIR;
> 	while (UHCHR & UHCHR_FSBIR)
> 		cpu_relax();
>
> 	/* This could be properly abstracted away through the
> 	   device data the day more machines are supported and
> 	   their differences can be figured out correctly. */
> 	if (machine_is_mainstone() || machine_is_myboard()) {
> 		/* setup Port1 GPIO pin. */
> 		pxa_gpio_mode( 88 | GPIO_ALT_FN_1_IN);	/* USBHPWR1 */
> 		pxa_gpio_mode( 89 | GPIO_ALT_FN_2_OUT);	/* USBHPEN1 */
>
> 		/* setup Port2 GPIO pin. */
> 		pxa_gpio_mode( 119 |GPIO_ALT_FN_1_IN);   /* USBHPWR2 */
> 		pxa_gpio_mode( 120 | GPIO_ALT_FN_2_OUT); /* USBHPEN2 */
>
> 		/* Set the Power Control Polarity Low and Power Sense
> 		   Polarity Low to active low. Supply power to USB ports. */
> 		UHCHR = (UHCHR | UHCHR_PCPL | UHCHR_PSPL) &
> 			~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
> 	}
>
> 	UHCHR &= ~UHCHR_SSE;
>
> 	UHCHIE = (UHCHIE_UPRIE | UHCHIE_RWIE);
> }
>
> Nicola Perrino
>
> Atlab S.r.l
>
> Il giorno mer, 16-11-2005 alle 17:14 +0000, David Vrabel ha scritto:
> > David Vrabel wrote:
> > > I have a PXA270 (C5 stepping) based board with two USB host port
> > > connectors.  The board is running kernel 2.6.14.
> > >
> > > Port 1 is wired to the PXA270's USB host port 1 (USBH_P<1>, USBH_N<1>,
> > > USBHPEN<1> and USBHPWR<1>) -- this port works.
> > >
> > > Port 2 is wired to the PXA270 USB 'client' port signals (USBC_P and
> > > USBC_N), USBHPEN<2> and USBHPWR<2> signals are not available on any
> > > external pin so bus power (Vbus) is controlled via GPIO 22 and
> > > over-current indictor is wired to GPIO 12 (though I currently not doing
> > > anything with this signal).  This port does not work.
> > >
> > > Platform specific code is as follows:
> > >
> > > 	GPSR(22) = GPIO_bit(22); /* enable Vbus on port 2 */
> > >
> > > 	/* route host port 2 to USBC_P/USBC_N signals and enable
> > >            pull downs on D+/D- */
> > > 	UP2OCR = UP2OCR_HXOE | UP2OCR_HXS | UP2OCR_DMPDE | UP2OCR_DPPDE;
> > >
> > > 	UHCHR = (UHCHR | UHCHR_PSPL) &
> > > 		~(UHCHR_SSEP1 | UHCHR_SSEP2 | UHCHR_SSEP3 | UHCHR_SSE);
> > >
> > > 	UHCRHDA |= UHCRHDA_NOCP;
> >
> > Got a solution back from our Intel FAE:  GPIO119 and GPIO120 must be
> > configured as USBHPWR<2> and USBHPEN<2> repectively.  Even though
> > they're not used and aren't even bonded out on some packages.
> >
> > David Vrabel
>
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