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List: linux-arm-kernel
Subject: Re: Problem with FIQ on at91rm9200
From: "Jean-Philippe Francois" <jp.francois () cynove ! com>
Date: 2004-05-19 8:33:31
Message-ID: 200405191033310109.0032E646 () smtp ! wanadoo ! fr
[Download RAW message or body]
it was "bad mode in data abort handler". The interesting thing is that the
> CPU is only in ABT_32 for a very short time within the data abort handler,
> just before it switches to SVC_32. So unless you generate a data or
> prefetch
> abort in ABT_32 its impossible be in a bad mode there.
>
> Aborts have a higher priority than normal IRQs and the CPU disables IRQs
> when
> executing an abort. So unless you enable IRQs before switching to SVC
> mode,
> there should be no way for an IRQ to happen while you're in ABT_32.
Agreed, but I am not touching any CPSR or SPSR register in my routine, except when \
doing the usual pc restore.
> Unless
> you make an error when restoring the CPSR from the SPSR and restore into
> ABT_32 with interrupts enabled ;-)
>
> But I guess you're not tinkering with the processor modes while executing
> the
> FIQ.
>
> There's one special thing about FIQ and ABT however: If FIQ and ABT happen
> "at
> the same time", the CPU first takes the ABT and then the FIQ immediately
> afterwards. So you're then in FIQ mode with the SPSR from ABT. Still, this
> should be absolutely safe unless you make wrong assumptions about SPSR
> being
> always SVC or USR and restore into the wrong mode.
>
So you have something like this :
User -> ABT32 : spsr = cpsr_usr cpsr=cpsr_abt32
ABT32 -> FIQ : spsr = cpsr_abt32
Then subs pc,lr,#4 restore the cpsr_abt32 right ?
I would understand a bad mod in data abort : FIQ 32.
But I am still looking for what could cause a bad mode in interrupt handler.
> regards,
> matthias
>
Thank you,
JP Francois
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