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List:       linux-arm-kernel
Subject:    Re: access memory sequence, cache or TLB first?
From:       Matthias Welwarsky <mwelwarsky () web ! de>
Date:       2002-12-01 9:17:01
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On Sunday 01 December 2002 03:50, Ziming Yuan wrote:
> Hi all,
>     I am now confused  with  the sequence of CPU access memory.  Which is
> the  first CPU will look at?  Cache or TLB?
>
> I think the sequence is:
>
>     1, CPU want to fetch data or instruction;
>     2, CPU have a look at  D-Cache or I-Cache;
>     3, If Cache hit, return the data or instruction;
>     4, If cache miss, CPU turn to MMU for help;
>     5, MMU first  look at TLB to see if the virtual address that CPU give
> had been translate before or not;
>     6, If  the virtual address had been translate, the  Physical address is
> out because  the relationship of VA--PA is recorded in TLB. , CPU will get
> the data or instruction         from  the physical address.
>     7, If no, MMU will work through  page tables to find the Physical
> address out, then fetch data or instruction from the physical address.
>           both at end of 6 or 7 TLB and cache will updated .
>
> I don't know whether this is right or not. Would u please point out the
> errors?  Thanks in advance!

AFAICS, this is correct for caches that use virtual addresses, like on the 
ARM.

>
> The most thing that confused me  is the graph in this URL:
>
>     http://ciips.ee.uwa.edu.au/~morris/CA406/TLB.html
>
> I don' t know why the sequence  is reversed?  Am I totally wrong? Can
> anybody here give me some advice?    Thanks again!!

Probably because the caches use physical addresses. In that case, you cannot 
look at the cache first because you need the physical address. That's why the 
cache comes after the address translation logic.

regards,
	matthias


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