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List: linux-arm-kernel
Subject: Re: Variable Latency I/O and write buffering?
From: Klaus Borchers <klaus.borchers () mobotix ! com>
Date: 2002-09-25 14:24:56
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On Wednesday 25 September 2002 12:57, you wrote:
> The StrongARM manuals suggest that there might be some situations in which
> one could turn on write buffering for variable latency I/O, but I've
> noticed nobody seems to do that (the 'b' bit in the map_desc structures I
> see for various architectures are always 0...).
>
> Does anyone know what the actual situations are in which I could do this,
> and would it possibly get me anywhere? I have a 16-bit I/O device on nCS3,
> and I'm just investigating options to see how fast I can talk to it.
>
> Also, I'm interested to know whether or not the SA will really do a "burst"
> to vl i/o -- the datasheet shows one, but other docs suggest maybe it will
> only do that for 32-bit wide devices.
I seems to work in my system.
I used the write-buffer for CS4 to access a 16 Bit device.
However, I have two chip-selects (CS4 and CS2) gated in hardware for the same
chip so I can use the non-bufferable CS2 for control register accesses and
the bufferable CS4 only for STMIA (write) accesses for bulk data transfer.
The trick here is that any read/write to a non bufferable location (CS2 for
the ethernet controller, but also any other register-access or chip-select),
will automatically force the write-buffer to drain first.
I also have explicit confirmation from intel that write-buffer transactions
are always executed in order.
There is one snag, however:
If you connect a slow peripheral using the write-buffer, DMA-Latencies will
increase dramatically (e.g. 8 write-buffer entries x 8 halfwords x 200ns =
12us). This might starve the LCD-DMA, or FIQ-Interrupts (they usually require
some HW-access, and this forces a drain on the write-buffer).
Regards, Klaus
--
Mobotix AG
Klaus Borchers
Luxemburgerstr. 6
D-67657 Kaiserslautern
Germany
Tel: +49 (631) 3033141
Fax: +49 (631) 3033190
E-Mail: Klaus.Borchers@mobotix.com
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