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Hi,
after checking the verilog definition i also found that some keyword are=20
missing in the definition of syntac highlighting for verilog.
I attach to the mail the corrected version for verilog (and system verilog =
as=20
well)
regards
stephane
=2D-=20
St=E9phane PETITHOMME
=2D--------------------------------------------------
e-mail:stephane.petithomme@certess.com
T=E9l: =A0+33 4 76 43 98 44
=46ax: =A0+33 4 76 43 03 57
Le Xenon
340 rue de l'Eygala
Centr'Alp
38430 Moirans
=46rance
This e-mail message is intended for the addressee(s) only and may contain=20
confidential and or privileged information. =A0If you are not the intended=
=20
recipient of this e-mail message, you should not read, copy, forward or=20
otherwise distribute or further disclose the information in it. If you have=
=20
received this e-mail message in error, please contact Certess SARL at=20
telephone number +33 4 76 43 98 50, fax number +33 4 76 43 03 57 or contact=
=20
the originator of this e-mail message via e-mail and delete all copies of=20
this message from your computer or network, thank you.
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Content-Type: text/xml;
charset="iso-8859-1";
name="systemverilog.xml"
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filename="systemverilog.xml"
- module
- macromodule
- endmodule
- task
- endtask
- function
- endfunction
- table
- endtable
- specify
- specparam
- endspecify
- case
- casex
- casez
- endcase
- fork
- join
- defparam
- default
- begin
- end
- if
- ifnone
- else
- forever
- while
- for
- wait
- repeat
- disable
- assign
- deassign
- force
- release
- always
- initial
- edge
- posedge
- negedge
- automatic
- cell
- config
- design
- endgenerate
- generate
- endprimitive
- genvar
- incdir
- include
- instance
- liblist
- library
- localparam
- noshowcancelled
- primitive
- pulsestyle_onevent
- pulsestyle_ondetect
- showcancelled
- use
- always_comb
- always_ff
- always_latch
- assert
- assume
- before
- bind
- bins
- binsof
- break
- class
- clocking
- constraint
- context
- continue
- cover
- covergroup
- coverpoint
- cross
- dist
- do
- endclass
- endclocking
- endgroup
- endinterface
- endpackage
- endprogram
- endproperty
- endsequence
- enum
- export
- extends
- extern
- expect
- final
- first_match
- foreach
- forkjoin
- iff
- ignore_bins
- illegal_bins
- import
- inside
- interface
- intersect
- join_any
- join_none
- matches
- modport
- new
- null
- package
- priority
- program
- property
- protected
- pure
- rand
- randc
- randsequence
- return
- sequence
- solve
- struct
- super
- tagged
- this
- throughout
- timeprecision
- timeunit
- type
- typedef
- union
- unique
- virtual
- wait_order
- with
- within
- strong0
- strong1
- pull0
- pull1
- weak0
- weak1
- highz0
- highz1
- small
- medium
- large
- pullup
- pulldown
- cmos
- rcmos
- nmos
- pmos
- rnmos
- rpmos
- and
- nand
- or
- nor
- xor
- xnor
- not
- buf
- tran
- rtran
- tranif0
- tranif1
- rtranif0
- rtranif1
- bufif0
- bufif1
- notif0
- notif1
- input
- output
- inout
- wire
- tri
- tri0
- tri1
- wand
- wor
- triand
- trior
- supply0
- supply1
- reg
- integer
- real
- realtime
- time
- vectored
- scalared
- trireg
- parameter
- event
- signed
- unsigned
- alias
- bit
- byte
- chandle
- const
- int
- local
- longint
- packed
- ref
- shortint
- shortreal
- static
- var
- void
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Content-Type: text/xml;
charset="iso-8859-1";
name="verilog.xml"
Content-Transfer-Encoding: 7bit
Content-Disposition: attachment;
filename="verilog.xml"
- module
- macromodule
- endmodule
- task
- endtask
- function
- endfunction
- table
- endtable
- specify
- specparam
- endspecify
- case
- casex
- casez
- endcase
- fork
- join
- defparam
- default
- begin
- end
- if
- ifnone
- else
- forever
- while
- for
- wait
- repeat
- disable
- assign
- deassign
- force
- release
- always
- initial
- edge
- posedge
- negedge
- automatic
- cell
- config
- design
- endgenerate
- generate
- endprimitive
- genvar
- incdir
- include
- instance
- liblist
- library
- localparam
- noshowcancelled
- primitive
- pulsestyle_onevent
- pulsestyle_ondetect
- showcancelled
- use
- strong0
- strong1
- pull0
- pull1
- weak0
- weak1
- highz0
- highz1
- small
- medium
- large
- pullup
- pulldown
- cmos
- rcmos
- nmos
- pmos
- rnmos
- rpmos
- and
- nand
- or
- nor
- xor
- xnor
- not
- buf
- tran
- rtran
- tranif0
- tranif1
- rtranif0
- rtranif1
- bufif0
- bufif1
- notif0
- notif1
- input
- output
- inout
- wire
- tri
- tri0
- tri1
- wand
- wor
- triand
- trior
- supply0
- supply1
- reg
- integer
- real
- realtime
- time
- vectored
- scalared
- trireg
- parameter
- event
- signed
- unsigned
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