From kwrite-devel  Wed Jun 13 14:38:47 2007
From: stephane PETITHOMME <stephane.petithomme () certess ! com>
Date: Wed, 13 Jun 2007 14:38:47 +0000
To: kwrite-devel
Subject: Re: Syntax Highlighting and SystemVerilog Hardware description
Message-Id: <200706131638.48034.stephane.petithomme () certess ! com>
X-MARC-Message: https://marc.info/?l=kwrite-devel&m=118174575526788
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Hi all,
Here attached is the syntax highlighting rules for SystemVerilog with exten=
ded=20
keyword.
I don't know where to setup the new related mimes types (for *.sv and *.sys=
v)=20
files at KDE level, if needed

Could one Kate developer add it to base code?
thanks

regards

stephane


On Wednesday 13 June 2007, Dominik Haumann wrote:
> On Wednesday 13 June 2007, Anders Lund wrote:
> > On Tuesday 12 June 2007, stephane PETITHOMME wrote:
> > > Hi all,
> > > I am using Kate (or Kdevelop) in my dayly work and i come to edit
> > > systemVerilog code. As I am also working on the grammar of this new
> > > hardware language, I'd like to add support for syntax highlighting for
> > > it to kate.
> > >
> > > Could i get some hint on how to process. I can do the work and send it
> > > back later.
> >
> > The syntax highlighting definitions are XML files in
> > KDEDIR/share/apps/katepart/syntax/<language>.xml
> >
> > There is a appendix in the kate handbook about the format, and an artic=
le
> > at http://www.kate-editor.org.
>
> http://kate-editor.org/article/writing_a_kate_highlighting_xml_file
> that is the link.
> kate-editor.org is still broken in that you can't click "next" or "2", see
> my other mail, so he will never find it by navigation.
>
> dominik



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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE language SYSTEM "language.dtd">
<language name="SystemVerilog" version="1.00" kateversion="2.4" section="Hardware" extensions="*.sv;*.sysv" mimetype="text/x-systemverilog-src" author="Yevgen Voronenko (ysv22@drexel.edu) modified Stephane Petithomme (stephane.petithomme@certess.com) " license="">
  <highlighting>
    <list name="keywords">
      <item> module </item>
      <item> macromodule </item>
      <item> endmodule </item>
      <item> task </item>
      <item> endtask </item>
      <item> function </item>
      <item> endfunction </item>
      <item> table </item>
      <item> endtable </item>
      <item> specify </item>
      <item> specparam </item>
      <item> endspecify </item>
      <item> case </item>
      <item> casex </item>
      <item> casez </item>
      <item> endcase </item>
      <item> fork </item>
      <item> join </item>

      <item> defparam </item>
      <item> default </item>
      <item> begin </item>
      <item> end </item>
      <item> if </item>
      <item> ifnone </item>
      <item> else </item>
      <item> forever </item>
      <item> while </item>
      <item> for </item>
      <item> wait </item>
      <item> repeat </item>
      <item> disable </item>

      <item> assign </item>
      <item> deassign </item>
      <item> force </item>
      <item> release </item>

      <item> always </item>
      <item> initial </item>
      <item> edge </item>
      <item> posedge </item>
      <item> negedge </item>

      <!-- System Verilog Specific -->
      <item> always_comb </item>
      <item> always_ff </item>
      <item> always_latch </item>
      <item> assert </item>
      <item> assume </item>
      <item> before </item>
      <item> bind </item>
      <item> bins </item>
      <item> binsof </item>
      <item> break </item>
      <item> class </item>
      <item> clocking </item>
      <item> constraint </item>
      <item> context </item>
      <item> continue </item>
      <item> cover </item>
      <item> covergroup </item>
      <item> coverpoint </item>
      <item> cross </item>
      <item> dist </item>
      <item> do </item>
      <item> endclass </item>
      <item> endclocking </item>
      <item> endgroup </item>
      <item> endinterface </item>
      <item> endpackage </item>
      <item> endprogram </item>
      <item> endproperty </item>
      <item> endsequence </item>
      <item> enum </item>
      <item> export </item>
      <item> extends </item>
      <item> extern </item>
      <item> expect </item>
      <item> final   </item>
      <item> first_match </item>
      <item> foreach </item>
      <item> forkjoin </item>
      <item> iff </item>
      <item> ignore_bins </item>
      <item> illegal_bins </item>
      <item> import </item>
      <item> inside </item>
      <item> interface </item>
      <item> intersect </item>
      <item> join_any </item>
      <item> join_none </item>
      <item> matches </item>
      <item> modport </item>
      <item> new </item>
      <item> null </item>
      <item> package </item>
      <item> priority </item>
      <item> program </item>
      <item> property </item>
      <item> protected </item>
      <item> pure </item>
      <item> rand </item>
      <item> randc </item>
      <item> randsequence </item>
      <item> return </item>
      <item> sequence </item>
      <item> solve </item>
      <item> struct </item>
      <item> super </item>
      <item> tagged </item>
      <item> this </item>
      <item> throughout </item>
      <item> timeprecision </item>
      <item> timeunit </item>
      <item> type </item>
      <item> typedef </item>
      <item> union </item>
      <item> unique </item>
      <item> virtual </item>
      <item> wait_order </item>
      <item> with </item>
      <item> within </item>
    </list>

    <list name="strength">
	<!-- drive strength supply0/supply1 omitted, its in types.. -->
	<item> strong0 </item>
	<item> strong1 </item>
	<item> pull0 </item>
	<item> pull1 </item>
	<item> weak0 </item>
	<item> weak1 </item>
	<item> highz0 </item>
	<item> highz1 </item>
	<!-- charge strength -->
	<item> small </item>
	<item> medium </item>
	<item> large </item>
    </list>

    <list name="gates">
       <item> pullup </item>
       <item> pulldown </item>
       <item> cmos </item>
       <item> rcmos </item>
       <item> nmos </item>
       <item> pmos </item>
       <item> rnmos </item>
       <item> rpmos </item>
       <item> and </item>
       <item> nand </item>
       <item> or </item>
       <item> nor </item>
       <item> xor </item>
       <item> xnor </item>
       <item> not </item>
       <item> buf </item>
       <item> tran </item>
       <item> rtran </item>
       <item> tranif0 </item>
       <item> tranif1 </item>
       <item> rtranif0 </item>
       <item> rtranif1 </item>
       <item> bufif0 </item>
       <item> bufif1 </item>
       <item> notif0 </item>
       <item> notif1 </item>
    </list>

    <list name="types">
      <!-- port direction -->
      <item> input </item>
      <item> output </item>
      <item> inout </item>
      <!-- net type -->
      <item> wire </item>
      <item> tri </item>
      <item> tri0 </item>
      <item> tri1 </item>
      <item> wand </item>
      <item> wor </item>
      <item> triand </item>
      <item> trior </item>
      <item> supply0 </item>
      <item> supply1 </item>
      <!-- reg/variable -->
      <item> reg </item>
      <item> integer </item>
      <item> real </item>
      <item> realtime </item>
      <item> time </item>
      <!-- modifier -->
      <item> vectored </item>
      <item> scalared </item>
      <item> trireg </item>
      <!-- other -->
      <item> parameter </item>
      <item> event </item>

      <!-- System Verilog Specific -->
      <item> alias </item>
      <item> bit </item>
      <item> byte </item>
      <item> chandle </item>
      <item> const </item>
      <item> int </item>
      <item> local </item>
      <item> longint </item>
      <item> packed </item>
      <item> ref </item>
      <item> shortint </item>
      <item> shortreal </item>
      <item> static </item>
      <item> var </item>
      <item> void </item>
    </list>

    <contexts>
      <context attribute="Normal Text" lineEndContext="#stay" name="Normal">
        <RegExpr attribute="Keyword" context="Block name" String="begin\ *:"/>
        <keyword attribute="Keyword" context="#stay" String="keywords" />
        <keyword attribute="Data Type" context="#stay" String="types" />
        <keyword attribute="Drive/charge strength" context="#stay" String="strength" />
        <keyword attribute="Gate instantiation" context="#stay" String="gates" />

        <RegExpr attribute="Normal Text" context="#stay" String="[a-zA-Z]+[\w$]*"/>
        <RegExpr attribute="Normal Text" context="#stay" String="\\[^ ]+ "/>

        <RegExpr attribute="Decimal" context="#stay" String="[\d_]*'d[\d_]+"/>
        <RegExpr attribute="Octal" context="#stay" String="[\d_]*'o[0-7xXzZ_]+"/>
        <RegExpr attribute="Hex" context="#stay" String="[\d_]*'h[\da-fA-FxXzZ_]+"/>
        <RegExpr attribute="Binary" context="#stay" String="[\d_]*'b[01_zZxX]+"/>
        <Float attribute="Float" context="#stay"/>
        <Int attribute="Integer" context="#stay" />

        <RegExpr attribute="Port connection" context="#stay" String="[^\w$]\.[a-zA-Z]+[\w$]*"/>

        <DetectChar attribute="String" context="String" char="&quot;"/>
        <Detect2Chars attribute="Comment" context="Commentar 1" char="/" char1="/"/>
        <Detect2Chars attribute="Comment" context="Commentar 2" char="/" char1="*"/>
        <AnyChar attribute="Symbol" context="#stay" String="!%&amp;()+,-&lt;=+/:;&gt;?[]^{|}~@"/>

        <StringDetect attribute="Comment" context="Some Context2" String="#if 0" insensitive="FALSE" firstNonSpace="true"/>

        <DetectChar attribute="Preprocessor" context="Preprocessor" char="`" column="0"/>
        <RegExpr attribute="Preprocessor" context="#stay" String="\`[a-zA-Z_]+\w*" />
        <RegExpr attribute="System Task" context="#stay" String="\$[a-zA-Z_]+\w*" />
        <RegExpr attribute="Delay" context="#stay" String="#[\d_]+" />
      </context>
      <context attribute="String" lineEndContext="#pop" name="String">
        <LineContinue attribute="String" context="Some Context"/>
        <HlCStringChar attribute="String Char" context="#stay"/>
        <DetectChar attribute="String" context="#pop" char="&quot;"/>
      </context>
      <context attribute="Comment" lineEndContext="#pop" name="Commentar 1">
        <RegExpr attribute="Alert" context="#stay" String="(FIXME|TODO)" />
      </context>
      <context attribute="Comment" lineEndContext="#stay" name="Commentar 2">
        <RegExpr attribute="Alert" context="#stay" String="(FIXME|TODO)" />
        <Detect2Chars attribute="Comment" context="#pop" char="*" char1="/"/>
      </context>
      <context attribute="Preprocessor" lineEndContext="#pop" name="Preprocessor">
        <LineContinue attribute="Preprocessor" context="Some Context"/>
        <RangeDetect attribute="Prep. Lib" context="#stay" char="&quot;" char1="&quot;"/>
        <RangeDetect attribute="Prep. Lib" context="#stay" char="&lt;" char1="&gt;"/>
        <Detect2Chars attribute="Comment" context="Commentar 1" char="/" char1="/"/>
        <Detect2Chars attribute="Comment" context="Commentar/Preprocessor" char="/" char1="*"/>
      </context>
      <context attribute="Comment" lineEndContext="#stay" name="Commentar/Preprocessor">
        <Detect2Chars attribute="Comment" context="#pop" char="*" char1="/" />
      </context>
      <context attribute="Normal Text" lineEndContext="#pop" name="Some Context"/>
      <context attribute="Comment" lineEndContext="#stay" name="Some Context2">
          <RegExpr attribute="Alert" context="#stay" String="(FIXME|TODO)" />
          <StringDetect attribute="Comment" context="#pop" String="#endif" firstNonSpace="true"/>
      </context>

      <context attribute="Block name" lineEndContext="#pop" name="Block name">
          <RegExpr attribute="Data Type" context="#pop" String="[^ ]+"/>
      </context>
    </contexts>

    <itemDatas>
      <itemData name="Normal Text" defStyleNum="dsNormal"/>
      <itemData name="Keyword"  defStyleNum="dsKeyword"/>
      <itemData name="Data Type"  defStyleNum="dsDataType"/>

      <itemData name="Decimal"  defStyleNum="dsBaseN"/>
      <itemData name="Octal"  defStyleNum="dsBaseN"/>
      <itemData name="Hex"  defStyleNum="dsBaseN"/>
      <itemData name="Binary"  defStyleNum="dsBaseN"/>
      <itemData name="Float"  defStyleNum="dsFloat"/>

      <itemData name="String"  defStyleNum="dsString"/>
      <itemData name="String Char"  defStyleNum="dsChar"/>
      <itemData name="Comment"  defStyleNum="dsComment"/>
      <itemData name="Alert"        defStyleNum="dsAlert" />
      <itemData name="Symbol"  defStyleNum="dsNormal"/>
      <itemData name="Preprocessor"  defStyleNum="dsOthers"/>
      <itemData name="Prep. Lib"  defStyleNum="dsFloat"/>
      <itemData name="System Task" defStyleNum="dsDataType"/>

      <itemData name="Integer" defStyleNum="dsDecVal"/>
      <itemData name="Delay" defStyleNum="dsBaseN"/>
      <itemData name="Block name" defStyleNum="dsDataType"/>
      <itemData name="Drive/charge strength" defStyleNum="dsBaseN"/>
      <itemData name="Gate instantiation" defStyleNum="dsDataType"/>
      <itemData name="Port connection" defStyleNum="dsDataType"/>
      </itemDatas>
  </highlighting>
  <general>
    <comments>
      <comment name="singleLine" start="//" />
      <comment name="multiLine" start="/*" end="*/" />
    </comments>
    <keywords casesensitive="1" />
  </general>
</language>

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