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List:       intel-wired-lan
Subject:    Re: [Intel-wired-lan] [PATCH v10 iwl-next 07/12] ice: Introduce ETH56G PHY model for E825C products
From:       "Pucha, HimasekharX Reddy" <himasekharx.reddy.pucha () intel ! com>
Date:       2024-05-17 7:38:06
Message-ID: CYYPR11MB8429776A2EACA1ED59C5F66DBDEE2 () CYYPR11MB8429 ! namprd11 ! prod ! outlook ! com
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> -----Original Message-----
> From: Intel-wired-lan <intel-wired-lan-bounces@osuosl.org> On Behalf Of K=
arol Kolacinski
> Sent: Wednesday, April 24, 2024 7:00 PM
> To: intel-wired-lan@lists.osuosl.org
> Cc: Michal Michalik <michal.michalik@intel.com>; Temerkhanov, Sergey <ser=
gey.temerkhanov@intel.com>; netdev@vger.kernel.org; Kubalewski, Arkadiusz <=
arkadiusz.kubalewski@intel.com>; Kolacinski, Karol <karol.kolacinski@intel.=
com>; Nguyen, Anthony L <anthony.l.nguyen@intel.com>; Kitszel, Przemyslaw <=
przemyslaw.kitszel@intel.com>; Keller, Jacob E <jacob.e.keller@intel.com>
> Subject: [Intel-wired-lan] [PATCH v10 iwl-next 07/12] ice: Introduce ETH5=
6G PHY model for E825C products
>
> From: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
>
> E825C products feature a new PHY model - ETH56G.
>
> Introduces all necessary PHY definitions, functions etc. for ETH56G PHY,
> analogous to E82X and E810 ones with addition of a few HW-specific
> functionalities for ETH56G like one-step timestamping.
>
> It ensures correct PTP initialization and operation for E825C products.
>
> Co-developed-by: Jacob Keller <jacob.e.keller@intel.com>
> Signed-off-by: Jacob Keller <jacob.e.keller@intel.com>
> Co-developed-by: Michal Michalik <michal.michalik@intel.com>
> Signed-off-by: Michal Michalik <michal.michalik@intel.com>
> Signed-off-by: Sergey Temerkhanov <sergey.temerkhanov@intel.com>
> Reviewed-by: Przemek Kitszel <przemyslaw.kitszel@intel.com>
> Reviewed-by: Arkadiusz Kubalewski <arkadiusz.kubalewski@intel.com>
> Co-developed-by: Karol Kolacinski <karol.kolacinski@intel.com>
> Signed-off-by: Karol Kolacinski <karol.kolacinski@intel.com>
> ---
> V7 -> V8: brought back P_REG_40B_HIGH_S due to 32 bit compatibility issue
> V4 -> V5: - removed inline in function types
>           - removed unnecessary ifdefs
>           - adjusted multiple returns of local vars at the end of functio=
n
> V1 -> V4: Adjusted bitslip calculations
>
>  drivers/net/ethernet/intel/ice/ice_common.c   |   10 +-
>  drivers/net/ethernet/intel/ice/ice_common.h   |    1 +
>  drivers/net/ethernet/intel/ice/ice_ptp.c      |  101 +-
>  drivers/net/ethernet/intel/ice/ice_ptp.h      |    1 +
>  .../net/ethernet/intel/ice/ice_ptp_consts.h   |  315 +++
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.c   | 2069 ++++++++++++++++-
>  drivers/net/ethernet/intel/ice/ice_ptp_hw.h   |  240 +-
>  drivers/net/ethernet/intel/ice/ice_sbq_cmd.h  |   10 +-
>  drivers/net/ethernet/intel/ice/ice_type.h     |   20 +-
>  9 files changed, 2613 insertions(+), 154 deletions(-)
>

Tested-by: Pucha Himasekhar Reddy <himasekharx.reddy.pucha@intel.com> (A Co=
ntingent worker at Intel)

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