[prev in list] [next in list] [prev in thread] [next in thread]
List: haiku-commits
Subject: [haiku-commits] haiku: hrev55667 - src/add-ons/kernel/drivers/graphics/intel_extreme headers/private
From: Rudolf Cornelissen <rudhaiku () gmail ! com>
Date: 2021-11-26 21:52:27
Message-ID: 20211126215227.E69D93FC2E () turing ! freelists ! org
[Download RAW message or body]
hrev55667 adds 1 changeset to branch 'master'
old head: 39e05c7d01484d9aed5438f0b4fef70f4f4728ff
new head: 03ed104900142edb52bff17af8ce4a14b755dfa0
overview: https://git.haiku-os.org/haiku/log/?qt=range&q=03ed10490014+%5E39e05c7d0148
----------------------------------------------------------------------------
03ed10490014: intel_extreme: enabled all known skylake gfx cards since they are pgm'd \
now
[ Rudolf Cornelissen <rudhaiku@gmail.com> ]
----------------------------------------------------------------------------
Revision: hrev55667
Commit: 03ed104900142edb52bff17af8ce4a14b755dfa0
URL: https://git.haiku-os.org/haiku/commit/?id=03ed10490014
Author: Rudolf Cornelissen <rudhaiku@gmail.com>
Date: Fri Nov 26 23:52:15 2021 UTC
----------------------------------------------------------------------------
4 files changed, 23 insertions(+), 16 deletions(-)
.../private/graphics/intel_extreme/intel_extreme.h | 16 ++++++++--------
src/add-ons/accelerants/intel_extreme/Ports.cpp | 2 +-
.../kernel/drivers/graphics/intel_extreme/driver.cpp | 9 +++------
.../drivers/graphics/intel_extreme/intel_extreme.cpp | 12 +++++++++++-
----------------------------------------------------------------------------
diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h \
b/headers/private/graphics/intel_extreme/intel_extreme.h index c210dd4044..6936b03607 \
100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -671,14 +671,14 @@ struct intel_free_graphics_memory {
#define DDI_BUF_CTL_C (0x4200 | REGS_NORTH_PIPE_AND_PORT)
#define DDI_BUF_CTL_D (0x4300 | REGS_NORTH_PIPE_AND_PORT)
#define DDI_BUF_CTL_E (0x4400 | REGS_NORTH_PIPE_AND_PORT)
-#define DDI_BUF_CTL_ENABLE (1 << 31)
-#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
-#define DDI_BUF_EMP_MASK (0xf << 24)
-#define DDI_BUF_PORT_REVERSAL (1 << 16)
-#define DDI_BUF_IS_IDLE (1 << 7)
-#define DDI_A_4_LANES (1 << 4)
-#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
-#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
+#define DDI_BUF_CTL_ENABLE (1 << 31)
+#define DDI_BUF_TRANS_SELECT(n) ((n) << 24)
+#define DDI_BUF_EMP_MASK (0xf << 24)
+#define DDI_BUF_PORT_REVERSAL (1 << 16)
+#define DDI_BUF_IS_IDLE (1 << 7)
+#define DDI_A_4_LANES (1 << 4)
+#define DDI_PORT_WIDTH(width) (((width) - 1) << 1)
+#define DDI_INIT_DISPLAY_DETECTED (1 << 0)
#define PIPE_DDI_FUNC_CTL_A (0x0400 | REGS_NORTH_PIPE_AND_PORT)
#define PIPE_DDI_FUNC_CTL_B (0x1400 | REGS_NORTH_PIPE_AND_PORT)
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp \
b/src/add-ons/accelerants/intel_extreme/Ports.cpp index 1124b019c1..e69c67bcc6 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -1536,7 +1536,7 @@ DigitalDisplayInterface::SetDisplayMode(display_mode* target, \
uint32 colorMode) skl_wrpll_params wrpll_params;
skl_ddi_calculate_wrpll(
target->timing.pixel_clock * 1000 /* in Hz */,
- 24000,//gInfo->shared_info->pll_info.reference_frequency, //fixme
+ gInfo->shared_info->pll_info.reference_frequency,
&wrpll_params);
fPipe->ConfigureClocksSKL(wrpll_params,
target->timing.pixel_clock,
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp \
b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp index \
a3ccaf08fa..3b326a284a 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp
@@ -105,9 +105,6 @@ const struct supported_device {
{0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"},
{0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"},
- {0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // testing..
- {0x1916, INTEL_MODEL_SKYM, "Skylake GT2"}, // testing..
-
#if 0
// The driver does not make any attempt to handle this modern hardware.
// Better let VESA/UEFI do it.
@@ -119,14 +116,15 @@ const struct supported_device {
{0x0157, INTEL_MODEL_VLVM, "ValleyView Mobile"},
// {0x1616, INTEL_MODEL_BDWM, "HD Graphics 5500 (Broadwell GT2)"},
+#endif
{0x1902, INTEL_MODEL_SKY, "Skylake GT1"},
{0x1906, INTEL_MODEL_SKYM, "Skylake GT1"},
{0x190a, INTEL_MODEL_SKYS, "Skylake GT1"},
{0x190b, INTEL_MODEL_SKY, "Skylake GT1"},
{0x190e, INTEL_MODEL_SKYM, "Skylake GT1"},
- {0x1912, INTEL_MODEL_SKY, "Skylake GT2"},
- {0x1916, INTEL_MODEL_SKYM, "Skylake GT2"},
+ {0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, //confirmed OK
+ {0x1916, INTEL_MODEL_SKYM, "Skylake GT2"}, //confirmed native mode panel OK
{0x191a, INTEL_MODEL_SKYS, "Skylake GT2"},
{0x191b, INTEL_MODEL_SKY, "Skylake GT2"},
{0x191d, INTEL_MODEL_SKY, "Skylake GT2"},
@@ -135,7 +133,6 @@ const struct supported_device {
{0x1926, INTEL_MODEL_SKYM, "Skylake GT3"},
{0x192a, INTEL_MODEL_SKYS, "Skylake GT3"},
{0x192b, INTEL_MODEL_SKY, "Skylake GT3"},
-#endif
};
int32 api_version = B_CUR_DRIVER_API_VERSION;
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp \
b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index \
a49eb23c10..5bcbb95ae5 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
@@ -453,7 +453,7 @@ intel_extreme_init(intel_info &info)
info.shared_info->single_head_locked = 1;
if (info.device_type.InFamily(INTEL_FAMILY_SER5)) {
- info.shared_info->pll_info.reference_frequency = 120000; // 120 MHz
+ info.shared_info->pll_info.reference_frequency = 120000;// 120 MHz
info.shared_info->pll_info.max_frequency = 350000;
// 350 MHz RAM DAC speed
info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
@@ -462,6 +462,16 @@ intel_extreme_init(intel_info &info)
info.shared_info->pll_info.max_frequency = 400000;
// 400 MHz RAM DAC speed
info.shared_info->pll_info.min_frequency = 20000; // 20 MHz
+ } else if ((info.device_type.HasDDI()) && (info.device_type.Generation() <= 8)) {
+ info.shared_info->pll_info.reference_frequency = 135000;// 135 MHz
+ info.shared_info->pll_info.max_frequency = 350000;
+ // 350 MHz RAM DAC speed
+ info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
+ } else if (info.device_type.Generation() == 9) {
+ info.shared_info->pll_info.reference_frequency = 24000; // 24 MHz
+ info.shared_info->pll_info.max_frequency = 350000;
+ // 350 MHz RAM DAC speed
+ info.shared_info->pll_info.min_frequency = 25000; // 25 MHz
} else {
info.shared_info->pll_info.reference_frequency = 48000; // 48 MHz
info.shared_info->pll_info.max_frequency = 350000;
[prev in list] [next in list] [prev in thread] [next in thread]
Configure |
About |
News |
Add a list |
Sponsored by KoreLogic