[prev in list] [next in list] [prev in thread] [next in thread]
List: gnuradio-discuss
Subject: [UHD] 4.6.0.0 Release Announcement
From: Aki Tomita <aki.tomita () ni ! com>
Date: 2023-11-17 16:18:03
Message-ID: BL0PR04MB4484B57991DE4A56AE22ED5AF5B7A () BL0PR04MB4484 ! namprd04 ! prod ! outlook ! com
[Download RAW message or body]
Hi All,
The UHD-4.6.0.0 release is now available.
This release adds phase repeatability, dual rate support, and lower samplin=
g rates for the NI Ettus USRP X440.
Tag for the UHD release:
https://github.com/EttusResearch/uhd/releases/tag/v4.6.0.0
Tag for the filesystem release:
https://github.com/EttusResearch/meta-ettus/releases/tag/v4.6.0.0
Installers for Windows and Fedora:
https://files.ettus.com/binaries/uhd/uhd_004.006.000.000-release/4.6.0.0/
PPA for Ubuntu:
https://launchpad.net/~ettusresearch/+archive/ubuntu/uhd
Thank you to everyone who has contributed by posting pull requests and fili=
ng bug reports.
Thanks,
Aki
CHANGELOG:
## 004.006.000.000
* ci
- only build docker images once per week
- propagate testLength to RF ATS
- replace deprecated ruamel.yaml methods
- use build farm for windows builds
* cmake
- Fix make_x410 and make_x440 targets
* deb
- copyright file update to eliminate errors and warnings
* docs
- X440: Add FBX to daughterboard list
- X440: Corrected web link syntax in FBX doc.
- X440: Add X440_X4_200 to image flavors
- X440: Add dual-rate documentation
* examples
- L band capture example using dual rate
* fpga
- ci: Add X440_X4_200 to pipelines
- lib: Allow buffering in eth_ipv4_chdr_adapter
- n3xx: Add CE clock
- rfnoc: Add clock info to backend ifc
- rfnoc: radio: Add clock index parameters
- tools: Add X440_X4_200 to X440 package
- x400: Add CE clock
- x400: Add X440 200 MHz variant with DDC/DUC
- x400: Split DRAM interface into two banks
- x400: Update PL DRAM speed bin
- x400: bump minor revision
- x400: pps_sync cleanup
- x400: propagate pps_sync changes
- x400: update signals to run on two domains
- x440: cpld: led control cleanup
- x440: remove extra synchronizer
* images
- bump x4xx fpga images
- update non-x4xx images
* lib
- rfnoc: Add clock info fields to client zero
- rfnoc: Add support for auto-clock discovery
- x4xx: Use auto clock ID in x400_radio_control
* mpm
- x440: Add lookup table for default MCR per DSP bandwidth
- x440: Multi-Tile Sync disabled when using dual rate
- x400: Align FPGA revision
- x400: match HDL PPS updates
- x400: make PRC a multiple of both rfdc rates
- fix timekeeper misalignment
* multi_usrp
- Added module_serial to info
* rfnoc
- Enable SEP throttle register
- image builder: Add clock index support to image builder
* utils
- init device with gpsdo sources in query_gpsdo_sensors
* x4xx
- Add support for auto clock ID
- FPGA designs now use a replay block per utilized DRAM bank
* x440
- Add support for using radio block specific master clock rates
- X4_440 and X4_1600 fpga image now contain 2 replay blocks
(number of ports per replay block halved compared to previous release)
[Attachment #3 (text/html)]
<html xmlns:v="urn:schemas-microsoft-com:vml" \
xmlns:o="urn:schemas-microsoft-com:office:office" \
xmlns:w="urn:schemas-microsoft-com:office:word" \
xmlns:m="http://schemas.microsoft.com/office/2004/12/omml" \
xmlns="http://www.w3.org/TR/REC-html40"> <head>
<meta http-equiv="Content-Type" content="text/html; charset=us-ascii">
<meta name="Generator" content="Microsoft Word 15 (filtered medium)">
<style><!--
/* Font Definitions */
@font-face
{font-family:"Cambria Math";
panose-1:2 4 5 3 5 4 6 3 2 4;}
@font-face
{font-family:Calibri;
panose-1:2 15 5 2 2 2 4 3 2 4;}
/* Style Definitions */
p.MsoNormal, li.MsoNormal, div.MsoNormal
{margin:0in;
font-size:11.0pt;
font-family:"Calibri",sans-serif;
mso-ligatures:standardcontextual;}
a:link, span.MsoHyperlink
{mso-style-priority:99;
color:#0563C1;
text-decoration:underline;}
span.EmailStyle17
{mso-style-type:personal-compose;
font-family:"Calibri",sans-serif;
color:windowtext;}
.MsoChpDefault
{mso-style-type:export-only;
font-family:"Calibri",sans-serif;}
@page WordSection1
{size:8.5in 11.0in;
margin:1.0in 1.0in 1.0in 1.0in;}
div.WordSection1
{page:WordSection1;}
--></style><!--[if gte mso 9]><xml>
<o:shapedefaults v:ext="edit" spidmax="1026" />
</xml><![endif]--><!--[if gte mso 9]><xml>
<o:shapelayout v:ext="edit">
<o:idmap v:ext="edit" data="1" />
</o:shapelayout></xml><![endif]-->
</head>
<body lang="EN-US" link="#0563C1" vlink="#954F72" style="word-wrap:break-word">
<div class="WordSection1">
<p class="MsoNormal">Hi All,<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">The UHD-4.6.0.0 release is now available.<o:p></o:p></p>
<p class="MsoNormal">This release adds phase repeatability, dual rate support, and \
lower sampling rates for the NI Ettus USRP X440.<o:p></o:p></p> <p \
class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Tag for the UHD \
release:<br> <a href="https://github.com/EttusResearch/uhd/releases/tag/v4.6.0.0">https://github.com/EttusResearch/uhd/releases/tag/v4.6.0.0</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Tag for the filesystem release:<o:p></o:p></p>
<p class="MsoNormal"><a \
href="https://github.com/EttusResearch/meta-ettus/releases/tag/v4.6.0.0">https://github.com/EttusResearch/meta-ettus/releases/tag/v4.6.0.0</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Installers for Windows and Fedora:<br>
<a href="https://files.ettus.com/binaries/uhd/uhd_004.006.000.000-release/4.6.0.0/">ht \
tps://files.ettus.com/binaries/uhd/uhd_004.006.000.000-release/4.6.0.0/</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">PPA for Ubuntu:<o:p></o:p></p>
<p class="MsoNormal"><a \
href="https://launchpad.net/~ettusresearch/+archive/ubuntu/uhd">https://launchpad.net/~ettusresearch/+archive/ubuntu/uhd</a><o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">Thank you to everyone who has contributed by posting pull \
requests and filing bug reports.<o:p></o:p></p> <p \
class="MsoNormal"><o:p> </o:p></p> <p class="MsoNormal">Thanks,<o:p></o:p></p>
<p class="MsoNormal">Aki<o:p></o:p></p>
<p class="MsoNormal"><o:p> </o:p></p>
<p class="MsoNormal">CHANGELOG:<o:p></o:p></p>
<p class="MsoNormal">## 004.006.000.000<o:p></o:p></p>
<p class="MsoNormal">* ci<o:p></o:p></p>
<p class="MsoNormal"> - only build docker images once per week<o:p></o:p></p>
<p class="MsoNormal"> - propagate testLength to RF ATS<o:p></o:p></p>
<p class="MsoNormal"> - replace deprecated ruamel.yaml methods<o:p></o:p></p>
<p class="MsoNormal"> - use build farm for windows builds<o:p></o:p></p>
<p class="MsoNormal">* cmake<o:p></o:p></p>
<p class="MsoNormal"> - Fix make_x410 and make_x440 targets<o:p></o:p></p>
<p class="MsoNormal">* deb<o:p></o:p></p>
<p class="MsoNormal"> - copyright file update to eliminate errors and \
warnings<o:p></o:p></p> <p class="MsoNormal">* docs<o:p></o:p></p>
<p class="MsoNormal"> - X440: Add FBX to daughterboard list<o:p></o:p></p>
<p class="MsoNormal"> - X440: Corrected web link syntax in FBX \
doc.<o:p></o:p></p> <p class="MsoNormal"> - X440: Add X440_X4_200 to image \
flavors<o:p></o:p></p> <p class="MsoNormal"> - X440: Add dual-rate \
documentation<o:p></o:p></p> <p class="MsoNormal">* examples<o:p></o:p></p>
<p class="MsoNormal"> - L band capture example using dual rate<o:p></o:p></p>
<p class="MsoNormal">* fpga<o:p></o:p></p>
<p class="MsoNormal"> - ci: Add X440_X4_200 to pipelines<o:p></o:p></p>
<p class="MsoNormal"> - lib: Allow buffering in \
eth_ipv4_chdr_adapter<o:p></o:p></p> <p class="MsoNormal"> - n3xx: Add CE \
clock<o:p></o:p></p> <p class="MsoNormal"> - rfnoc: Add clock info to backend \
ifc<o:p></o:p></p> <p class="MsoNormal"> - rfnoc: radio: Add clock index \
parameters<o:p></o:p></p> <p class="MsoNormal"> - tools: Add X440_X4_200 to \
X440 package<o:p></o:p></p> <p class="MsoNormal"> - x400: Add CE \
clock<o:p></o:p></p> <p class="MsoNormal"> - x400: Add X440 200 MHz variant \
with DDC/DUC<o:p></o:p></p> <p class="MsoNormal"> - x400: Split DRAM interface \
into two banks<o:p></o:p></p> <p class="MsoNormal"> - x400: Update PL DRAM \
speed bin<o:p></o:p></p> <p class="MsoNormal"> - x400: bump minor \
revision<o:p></o:p></p> <p class="MsoNormal"> - x400: pps_sync \
cleanup<o:p></o:p></p> <p class="MsoNormal"> - x400: propagate pps_sync \
changes<o:p></o:p></p> <p class="MsoNormal"> - x400: update signals to run on \
two domains<o:p></o:p></p> <p class="MsoNormal"> - x440: cpld: led control \
cleanup<o:p></o:p></p> <p class="MsoNormal"> - x440: remove extra \
synchronizer<o:p></o:p></p> <p class="MsoNormal">* images<o:p></o:p></p>
<p class="MsoNormal"> - bump x4xx fpga images<o:p></o:p></p>
<p class="MsoNormal"> - update non-x4xx images<o:p></o:p></p>
<p class="MsoNormal">* lib<o:p></o:p></p>
<p class="MsoNormal"> - rfnoc: Add clock info fields to client \
zero<o:p></o:p></p> <p class="MsoNormal"> - rfnoc: Add support for auto-clock \
discovery<o:p></o:p></p> <p class="MsoNormal"> - x4xx: Use auto clock ID in \
x400_radio_control<o:p></o:p></p> <p class="MsoNormal">* mpm<o:p></o:p></p>
<p class="MsoNormal"> - x440: Add lookup table for default MCR per DSP \
bandwidth<o:p></o:p></p> <p class="MsoNormal"> - x440: Multi-Tile Sync disabled \
when using dual rate<o:p></o:p></p> <p class="MsoNormal"> - x400: Align FPGA \
revision<o:p></o:p></p> <p class="MsoNormal"> - x400: match HDL PPS \
updates<o:p></o:p></p> <p class="MsoNormal"> - x400: make PRC a multiple of \
both rfdc rates<o:p></o:p></p> <p class="MsoNormal"> - fix timekeeper \
misalignment<o:p></o:p></p> <p class="MsoNormal">* multi_usrp<o:p></o:p></p>
<p class="MsoNormal"> - Added module_serial to info<o:p></o:p></p>
<p class="MsoNormal">* rfnoc<o:p></o:p></p>
<p class="MsoNormal"> - Enable SEP throttle register<o:p></o:p></p>
<p class="MsoNormal"> - image builder: Add clock index support to image \
builder<o:p></o:p></p> <p class="MsoNormal">* utils<o:p></o:p></p>
<p class="MsoNormal"> - init device with gpsdo sources in \
query_gpsdo_sensors<o:p></o:p></p> <p class="MsoNormal">* x4xx<o:p></o:p></p>
<p class="MsoNormal"> - Add support for auto clock ID<o:p></o:p></p>
<p class="MsoNormal"> - FPGA designs now use a replay block per utilized DRAM \
bank<o:p></o:p></p> <p class="MsoNormal">* x440<o:p></o:p></p>
<p class="MsoNormal"> - Add support for using radio block specific master clock \
rates<o:p></o:p></p> <p class="MsoNormal"> - X4_440 and X4_1600 fpga image now \
contain 2 replay blocks<o:p></o:p></p> <p class="MsoNormal"> \
(number of ports per replay block halved compared to previous release)<o:p></o:p></p> \
<p class="MsoNormal"><o:p> </o:p></p> </div>
</body>
</html>
[prev in list] [next in list] [prev in thread] [next in thread]
Configure |
About |
News |
Add a list |
Sponsored by KoreLogic