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List: gnuradio-commit
Subject: [Commit-gnuradio] r5170 - in gnuradio/branches/developers/thottelt: inband/usrp/fpga/inband_lib simu
From: thottelt () gnuradio ! org
Date: 2007-04-28 0:59:12
Message-ID: 20070428005912.730FE38005F () nyquist ! gnuradio ! org
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Author: thottelt
Date: 2007-04-27 18:59:11 -0600 (Fri, 27 Apr 2007)
New Revision: 5170
Modified:
gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
gnuradio/branches/developers/thottelt/simulations/tx.mpf
Log:
still broken
Modified: gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
===================================================================
--- gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 2007-04-28 \
00:58:00 UTC (rev 5169)
+++ gnuradio/branches/developers/thottelt/inband/usrp/fpga/inband_lib/usb_packet_fifo2.v 2007-04-28 \
00:59:11 UTC (rev 5170) @@ -53,7 +53,7 @@
assign read_data = fifo_rdata[fifo_rselect] ;
/* Figure out if we're all empty */
- assign tx_empty = !(~fifo_rempty);
+ assign tx_empty = !(~fifo_rempty) ;
/* Increment fifo_rselect here */
always @(posedge fpga_clock)
@@ -74,32 +74,18 @@
if (reset)
begin
fifo_wselect <= {2**LOG2_N{1'b0}} ;
- //fifo_we <= {2**LOG2_N{1'b0}} ;
second_half <= 0;
end
if (fifo_wfull[fifo_wselect])
fifo_wselect <= fifo_wselect + 1 ;
- /*if (write_enable)
+ if (write_enable)
begin
- if (second_half)
- begin
- fifo_wdata[fifo_wselect] <= {msb_usbdata, write_data} ;
- fifo_we[fifo_wselect] <= 1 ;
- second_half <= 0 ;
- end
- else
- begin
+ second_half = ~second_half ;
+ if (!second_half)
msb_usbdata <= write_data ;
- fifo_we[fifo_wselect] <= 0 ;
- second_half <= 1 ;
- end
end
- else
- begin
- fifo_we[fifo_wselect] <= 0 ;
- end*/
end
/* Generate all the single packet FIFOs */
@@ -108,8 +94,8 @@
begin : generate_single_packet_fifos
assign fifo_re[i] = (fifo_rselect == i) ? read_enable : 1'b0 ;
assign fifo_resets[i] = (fifo_rselect == i) ? skip_packet : 1'b0 ;
- assign fifo_we[i] = (fifo_wselect == i) ? write_enable : 1'b0 ;
- assign fifo_wdata[i] = write_data;
+ assign fifo_we[i] = (fifo_wselect == i) ? write_enable & ~second_half : \
1'b0 ; + assign fifo_wdata[i] = {msb_usbdata, write_data} ;
fifo_512 single_packet_fifo(.wrclk ( usb_clock ),
.rdclk ( fpga_clock ),
.aclr ( fifo_resets[i] ),
Modified: gnuradio/branches/developers/thottelt/simulations/tx.mpf
===================================================================
--- gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-28 00:58:00 UTC \
(rev 5169)
+++ gnuradio/branches/developers/thottelt/simulations/tx.mpf 2007-04-28 00:59:11 UTC \
(rev 5170) @@ -253,9 +253,9 @@
Project_File_3 = ./fake_fx2.v
Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177707503 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 \
compile_to work vlog_options {} compile_order 11 cover_expr 0 dont_compile 0 \
cover_stmt 0 Project_File_4 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo2.v
-Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177718354 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 \
compile_to work vlog_options {} compile_order 14 cover_expr 0 dont_compile 0 \
cover_stmt 0 +Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog \
group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder \
{Top Level} last_compile 1177721745 cover_branch 0 vlog_noload 0 vlog_enable0In 0 \
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions \
{} vlog_options {} compile_to work vlog_upper 0 compile_order 14 dont_compile 0 \
cover_expr 0 cover_stmt 0 Project_File_5 = \
../inband/usrp/fpga/inband_lib/usb_fifo_reader.v
-Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177712049 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 \
compile_to work vlog_options {} compile_order 8 cover_expr 0 dont_compile 0 \
cover_stmt 0 +Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog \
group_id 0 cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder \
{Top Level} last_compile 1177718984 cover_branch 0 vlog_noload 0 vlog_enable0In 0 \
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions \
{} vlog_options {} compile_to work vlog_upper 0 compile_order 8 dont_compile 0 \
cover_expr 0 cover_stmt 0 Project_File_6 = \
../inband/usrp/fpga/inband_lib/chan_fifo_reader.v Project_File_P_6 = cover_toggle 0 \
vlog_protect 0 file_type verilog group_id 0 cover_exttoggle 0 cover_cond 0 \
vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} last_compile 1177273481 \
cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt 0 vlog_vopt 0 \
vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options {} compile_to \
work vlog_upper 0 compile_order 6 dont_compile 0 cover_expr 0 cover_stmt 0 \
Project_File_7 = ../inband/usrp/fpga/inband_lib/tx_buffer_inband.v @@ -264,18 +264,18 \
@@ Project_File_P_8 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177273499 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 \
compile_to work vlog_options {} compile_order 1 cover_expr 0 dont_compile 0 \
cover_stmt 0 Project_File_9 = ./usb_packet_fifo_test.v
Project_File_P_9 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177365360 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 0 dont_compile 0 cover_expr 0 \
cover_stmt 0
-Project_File_10 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
-Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177365862 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 5 dont_compile 0 cover_expr 0 \
cover_stmt 0
-Project_File_11 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
-Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177366318 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 7 dont_compile 0 cover_expr 0 \
cover_stmt 0
-Project_File_12 = ./tx_buffer_test.v
-Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177348942 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 3 dont_compile 0 cover_expr 0 \
cover_stmt 0 +Project_File_10 = ./tx_buffer_test.v
+Project_File_P_10 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177348942 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 3 dont_compile 0 cover_expr 0 \
cover_stmt 0 +Project_File_11 = ../inband/usrp/fpga/inband_lib/usb_packet_fifo.v
+Project_File_P_11 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177365862 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 5 dont_compile 0 cover_expr 0 \
cover_stmt 0 +Project_File_12 = ../inband/usrp/fpga/inband_lib/data_packet_fifo.v
+Project_File_P_12 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177366318 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 7 dont_compile 0 cover_expr 0 \
cover_stmt 0 Project_File_13 = ../inband/usrp/fpga/sdr_lib/strobe_gen.v
Project_File_P_13 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1175362687 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions {} ood 0 vlog_upper 0 \
compile_to work vlog_options {} compile_order 9 cover_expr 0 dont_compile 0 \
cover_stmt 0
-Project_File_14 = ./usb_fifo_reader_test.v
-Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177713127 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 2 dont_compile 0 cover_expr 0 \
cover_stmt 0
-Project_File_15 = ../inband/usrp/fpga/megacells/fifo_512.v
-Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177705117 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 13 dont_compile 0 cover_expr 0 \
cover_stmt 0 +Project_File_14 = ../inband/usrp/fpga/megacells/fifo_512.v
+Project_File_P_14 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177705117 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 13 dont_compile 0 cover_expr 0 \
cover_stmt 0 +Project_File_15 = ./usb_fifo_reader_test.v
+Project_File_P_15 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0 \
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top Level} \
last_compile 1177713127 cover_branch 0 vlog_noload 0 vlog_enable0In 0 vlog_disableopt \
0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0 vlog_0InOptions {} vlog_options \
{} compile_to work vlog_upper 0 compile_order 2 dont_compile 0 cover_expr 0 \
cover_stmt 0 Project_Sim_Count = 0
Project_Folder_Count = 0
Echo_Compile_Output = 0
@@ -305,6 +305,6 @@
XML_CustomDoubleClick =
LOGFILE_DoubleClick = Edit
LOGFILE_CustomDoubleClick =
-EditorState = {tabbed horizontal 1} {Z:/wc/simulations/usb_packet_fifo2_test.v 0 0} \
{Z:/wc/simulations/fake_fx2.v 0 1} +EditorState = {tabbed horizontal 1} \
{Z:/wc/simulations/usb_packet_fifo2_test.v 0 1} {Z:/wc/simulations/fake_fx2.v 0 0} \
Project_Major_Version = 6 Project_Minor_Version = 1
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