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List:       git-commits-head
Subject:    KVM: x86: VMX: __kvm_apic_update_irr must update the IRR atomically
From:       Linux Kernel Mailing List <linux-kernel () vger ! kernel ! org>
Date:       2023-07-30 19:43:52
Message-ID: git-mailbomb-linux-master-514946d1436341bae57f647ee633cef5edb19ee2 () kernel ! org
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Commit:     514946d1436341bae57f647ee633cef5edb19ee2
Parent:     6eaae198076080886b9e7d57f4ae06fa782f90ef
Refname:    refs/heads/master
Web:        https://git.kernel.org/torvalds/c/514946d1436341bae57f647ee633cef5edb19ee2
Author:     Maxim Levitsky <mlevitsk@redhat.com>
AuthorDate: Wed Jul 26 16:59:43 2023 +0300
Committer:  Paolo Bonzini <pbonzini@redhat.com>
CommitDate: Sat Jul 29 11:05:24 2023 -0400

    KVM: x86: VMX: __kvm_apic_update_irr must update the IRR atomically
    
    If APICv is inhibited, then IPIs from peer vCPUs are done by
    atomically setting bits in IRR.
    
    This means, that when __kvm_apic_update_irr copies PIR to IRR,
    it has to modify IRR atomically as well.
    
    Signed-off-by: Maxim Levitsky <mlevitsk@redhat.com>
    Message-Id: <20230726135945.260841-2-mlevitsk@redhat.com>
    Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 arch/x86/kvm/lapic.c | 20 +++++++++++++-------
 1 file changed, 13 insertions(+), 7 deletions(-)

diff --git a/arch/x86/kvm/lapic.c b/arch/x86/kvm/lapic.c
index 113ca9661ab21..b17b37e4d4fcd 100644
--- a/arch/x86/kvm/lapic.c
+++ b/arch/x86/kvm/lapic.c
@@ -637,16 +637,22 @@ bool __kvm_apic_update_irr(u32 *pir, void *regs, int *max_irr)
 	*max_irr = -1;
 
 	for (i = vec = 0; i <= 7; i++, vec += 32) {
+		u32 *p_irr = (u32 *)(regs + APIC_IRR + i * 0x10);
+
+		irr_val = *p_irr;
 		pir_val = READ_ONCE(pir[i]);
-		irr_val = *((u32 *)(regs + APIC_IRR + i * 0x10));
+
 		if (pir_val) {
+			pir_val = xchg(&pir[i], 0);
+
 			prev_irr_val = irr_val;
-			irr_val |= xchg(&pir[i], 0);
-			*((u32 *)(regs + APIC_IRR + i * 0x10)) = irr_val;
-			if (prev_irr_val != irr_val) {
-				max_updated_irr =
-					__fls(irr_val ^ prev_irr_val) + vec;
-			}
+			do {
+				irr_val = prev_irr_val | pir_val;
+			} while (prev_irr_val != irr_val &&
+				 !try_cmpxchg(p_irr, &prev_irr_val, irr_val));
+
+			if (prev_irr_val != irr_val)
+				max_updated_irr = __fls(irr_val ^ prev_irr_val) + vec;
 		}
 		if (irr_val)
 			*max_irr = __fls(irr_val) + vec;
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