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List: git-commits-head
Subject: MIPS: Only allow Cavium OCTEON to be configured for boards that support it
From: Linux Kernel Mailing List <linux-kernel () vger ! kernel ! org>
Date: 2009-02-28 2:01:13
Message-ID: 200902280201.n1S21DsO011499 () hera ! kernel ! org
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Gitweb: http://git.kernel.org/git/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=5e6833892e7b745b164bae8b2edb75ccd1bee866
Commit: 5e6833892e7b745b164bae8b2edb75ccd1bee866
Parent: 64e71303e44f3697e4568147caa966de74bdb4fb
Author: David Daney <ddaney@caviumnetworks.com>
AuthorDate: Mon Feb 2 11:30:59 2009 -0800
Committer: Ralf Baechle <ralf@linux-mips.org>
CommitDate: Fri Feb 27 17:56:34 2009 +0000
MIPS: Only allow Cavium OCTEON to be configured for boards that support it
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
CC: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
---
arch/mips/Kconfig | 8 ++++++--
1 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index 600eef3..cb76d16 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -603,7 +603,7 @@ config CAVIUM_OCTEON_SIMULATOR
select SYS_SUPPORTS_64BIT_KERNEL
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
- select CPU_CAVIUM_OCTEON
+ select SYS_HAS_CPU_CAVIUM_OCTEON
help
The Octeon simulator is software performance model of the Cavium
Octeon Processor. It supports simulating Octeon processors on x86
@@ -618,7 +618,7 @@ config CAVIUM_OCTEON_REFERENCE_BOARD
select SYS_SUPPORTS_BIG_ENDIAN
select SYS_SUPPORTS_HIGHMEM
select SYS_HAS_EARLY_PRINTK
- select CPU_CAVIUM_OCTEON
+ select SYS_HAS_CPU_CAVIUM_OCTEON
select SWAP_IO_SPACE
help
This option supports all of the Octeon reference boards from Cavium
@@ -1234,6 +1234,7 @@ config CPU_SB1
config CPU_CAVIUM_OCTEON
bool "Cavium Octeon processor"
+ depends on SYS_HAS_CPU_CAVIUM_OCTEON
select IRQ_CPU
select IRQ_CPU_OCTEON
select CPU_HAS_PREFETCH
@@ -1314,6 +1315,9 @@ config SYS_HAS_CPU_RM9000
config SYS_HAS_CPU_SB1
bool
+config SYS_HAS_CPU_CAVIUM_OCTEON
+ bool
+
#
# CPU may reorder R->R, R->W, W->R, W->W
# Reordering beyond LL and SC is handled in WEAK_REORDERING_BEYOND_LLSC
--
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