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List:       gcc-patches
Subject:    Re: [PATCH] RISC-V: Add vsll.vv C++ API tests
From:       Kito Cheng via Gcc-patches <gcc-patches () gcc ! gnu ! org>
Date:       2023-01-31 16:49:22
Message-ID: CA+yXCZDyFCLpnnWarj0QwOUDcZtovuPk4RgpxqPFrN3XHHQvrA () mail ! gmail ! com
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committed, thanks!

On Tue, Jan 31, 2023 at 9:01 PM <juzhe.zhong@rivai.ai> wrote:
> 
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> gcc/testsuite/ChangeLog:
> 
> * g++.target/riscv/rvv/base/vsll_vv-1.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv-2.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv-3.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_mu-1.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_mu-2.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_mu-3.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tu-1.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tu-2.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tu-3.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tum-1.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tum-2.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tum-3.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tumu-1.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tumu-2.C: New test.
> * g++.target/riscv/rvv/base/vsll_vv_tumu-3.C: New test.
> 
> ---
> .../g++.target/riscv/rvv/base/vsll_vv-1.C     | 578 ++++++++++++++++++
> .../g++.target/riscv/rvv/base/vsll_vv-2.C     | 578 ++++++++++++++++++
> .../g++.target/riscv/rvv/base/vsll_vv-3.C     | 578 ++++++++++++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_mu-1.C  | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_mu-2.C  | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_mu-3.C  | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_tu-1.C  | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_tu-2.C  | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_tu-3.C  | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_tum-1.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_tum-2.C | 292 +++++++++
> .../g++.target/riscv/rvv/base/vsll_vv_tum-3.C | 292 +++++++++
> .../riscv/rvv/base/vsll_vv_tumu-1.C           | 292 +++++++++
> .../riscv/rvv/base/vsll_vv_tumu-2.C           | 292 +++++++++
> .../riscv/rvv/base/vsll_vv_tumu-3.C           | 292 +++++++++
> 15 files changed, 5238 insertions(+)
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-3.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-1.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-2.C
> create mode 100644 gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-3.C
> 
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-1.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-1.C new file mode 100644
> index 00000000000..d9bf605cf95
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-1.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll(vint8m1_t op1,vuint8m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll(vint8m2_t op1,vuint8m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll(vint8m4_t op1,vuint8m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll(vint8m8_t op1,vuint8m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll(vint16m1_t op1,vuint16m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll(vint16m2_t op1,vuint16m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll(vint16m4_t op1,vuint16m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll(vint16m8_t op1,vuint16m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll(vint32m1_t op1,vuint32m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll(vint32m2_t op1,vuint32m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll(vint32m4_t op1,vuint32m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll(vint32m8_t op1,vuint32m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll(vint64m1_t op1,vuint64m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll(vint64m2_t op1,vuint64m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll(vint64m4_t op1,vuint64m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll(vint64m8_t op1,vuint64m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll(vuint8m1_t op1,vuint8m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll(vuint8m2_t op1,vuint8m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll(vuint8m4_t op1,vuint8m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll(vuint8m8_t op1,vuint8m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll(vuint16m1_t op1,vuint16m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll(vuint16m2_t op1,vuint16m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll(vuint16m4_t op1,vuint16m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll(vuint16m8_t op1,vuint16m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll(vuint32m1_t op1,vuint32m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll(vuint32m2_t op1,vuint32m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll(vuint32m4_t op1,vuint32m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll(vuint32m8_t op1,vuint32m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll(vuint64m1_t op1,vuint64m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll(vuint64m2_t op1,vuint64m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll(vuint64m4_t op1,vuint64m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll(vuint64m8_t op1,vuint64m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,vl);
> +}
> +
> +
> +vint8mf8_t test___riscv_vsll(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll(vbool16_t mask,vint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll(vbool32_t mask,vint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll(vbool16_t mask,vint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll(vbool64_t mask,vint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll(vbool32_t mask,vint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll(vbool16_t mask,vint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll(vbool16_t mask,vuint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll(vbool8_t mask,vuint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll(vbool4_t mask,vuint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll(vbool2_t mask,vuint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll(vbool32_t mask,vuint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll(vbool16_t mask,vuint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll(vbool8_t mask,vuint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll(vbool4_t mask,vuint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll(vbool64_t mask,vuint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll(vbool32_t mask,vuint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll(vbool16_t mask,vuint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll(vbool8_t mask,vuint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-2.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-2.C new file mode 100644
> index 00000000000..093c507c586
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-2.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll(vint8m1_t op1,vuint8m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll(vint8m2_t op1,vuint8m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll(vint8m4_t op1,vuint8m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll(vint8m8_t op1,vuint8m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll(vint16m1_t op1,vuint16m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll(vint16m2_t op1,vuint16m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll(vint16m4_t op1,vuint16m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll(vint16m8_t op1,vuint16m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll(vint32m1_t op1,vuint32m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll(vint32m2_t op1,vuint32m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll(vint32m4_t op1,vuint32m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll(vint32m8_t op1,vuint32m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll(vint64m1_t op1,vuint64m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll(vint64m2_t op1,vuint64m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll(vint64m4_t op1,vuint64m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll(vint64m8_t op1,vuint64m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll(vuint8m1_t op1,vuint8m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll(vuint8m2_t op1,vuint8m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll(vuint8m4_t op1,vuint8m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll(vuint8m8_t op1,vuint8m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll(vuint16m1_t op1,vuint16m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll(vuint16m2_t op1,vuint16m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll(vuint16m4_t op1,vuint16m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll(vuint16m8_t op1,vuint16m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll(vuint32m1_t op1,vuint32m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll(vuint32m2_t op1,vuint32m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll(vuint32m4_t op1,vuint32m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll(vuint32m8_t op1,vuint32m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll(vuint64m1_t op1,vuint64m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll(vuint64m2_t op1,vuint64m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll(vuint64m4_t op1,vuint64m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll(vuint64m8_t op1,vuint64m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,31);
> +}
> +
> +
> +vint8mf8_t test___riscv_vsll(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll(vbool16_t mask,vint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll(vbool32_t mask,vint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll(vbool16_t mask,vint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll(vbool64_t mask,vint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll(vbool32_t mask,vint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll(vbool16_t mask,vint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll(vbool16_t mask,vuint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll(vbool8_t mask,vuint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll(vbool4_t mask,vuint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll(vbool2_t mask,vuint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll(vbool32_t mask,vuint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll(vbool16_t mask,vuint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll(vbool8_t mask,vuint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll(vbool4_t mask,vuint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll(vbool64_t mask,vuint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll(vbool32_t mask,vuint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll(vbool16_t mask,vuint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll(vbool8_t mask,vuint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-3.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-3.C new file mode 100644
> index 00000000000..16034a7d70f
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv-3.C
> @@ -0,0 +1,578 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll(vint8mf8_t op1,vuint8mf8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll(vint8mf4_t op1,vuint8mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll(vint8mf2_t op1,vuint8mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll(vint8m1_t op1,vuint8m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll(vint8m2_t op1,vuint8m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll(vint8m4_t op1,vuint8m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll(vint8m8_t op1,vuint8m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll(vint16mf4_t op1,vuint16mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll(vint16mf2_t op1,vuint16mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll(vint16m1_t op1,vuint16m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll(vint16m2_t op1,vuint16m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll(vint16m4_t op1,vuint16m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll(vint16m8_t op1,vuint16m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll(vint32mf2_t op1,vuint32mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll(vint32m1_t op1,vuint32m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll(vint32m2_t op1,vuint32m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll(vint32m4_t op1,vuint32m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll(vint32m8_t op1,vuint32m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll(vint64m1_t op1,vuint64m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll(vint64m2_t op1,vuint64m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll(vint64m4_t op1,vuint64m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll(vint64m8_t op1,vuint64m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll(vuint8mf8_t op1,vuint8mf8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll(vuint8mf4_t op1,vuint8mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll(vuint8mf2_t op1,vuint8mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll(vuint8m1_t op1,vuint8m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll(vuint8m2_t op1,vuint8m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll(vuint8m4_t op1,vuint8m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll(vuint8m8_t op1,vuint8m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll(vuint16mf4_t op1,vuint16mf4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll(vuint16mf2_t op1,vuint16mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll(vuint16m1_t op1,vuint16m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll(vuint16m2_t op1,vuint16m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll(vuint16m4_t op1,vuint16m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll(vuint16m8_t op1,vuint16m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll(vuint32mf2_t op1,vuint32mf2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll(vuint32m1_t op1,vuint32m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll(vuint32m2_t op1,vuint32m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll(vuint32m4_t op1,vuint32m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll(vuint32m8_t op1,vuint32m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll(vuint64m1_t op1,vuint64m1_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll(vuint64m2_t op1,vuint64m2_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll(vuint64m4_t op1,vuint64m4_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll(vuint64m8_t op1,vuint64m8_t shift,size_t vl)
> +{
> +    return __riscv_vsll(op1,shift,32);
> +}
> +
> +
> +vint8mf8_t test___riscv_vsll(vbool64_t mask,vint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll(vbool32_t mask,vint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll(vbool16_t mask,vint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll(vbool8_t mask,vint8m1_t op1,vuint8m1_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll(vbool4_t mask,vint8m2_t op1,vuint8m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll(vbool2_t mask,vint8m4_t op1,vuint8m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll(vbool1_t mask,vint8m8_t op1,vuint8m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll(vbool64_t mask,vint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll(vbool32_t mask,vint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll(vbool16_t mask,vint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll(vbool8_t mask,vint16m2_t op1,vuint16m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll(vbool4_t mask,vint16m4_t op1,vuint16m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll(vbool2_t mask,vint16m8_t op1,vuint16m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll(vbool64_t mask,vint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll(vbool32_t mask,vint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll(vbool16_t mask,vint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll(vbool8_t mask,vint32m4_t op1,vuint32m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll(vbool4_t mask,vint32m8_t op1,vuint32m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll(vbool64_t mask,vint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll(vbool32_t mask,vint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll(vbool16_t mask,vint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll(vbool8_t mask,vint64m8_t op1,vuint64m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll(vbool64_t mask,vuint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll(vbool32_t mask,vuint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll(vbool16_t mask,vuint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll(vbool8_t mask,vuint8m1_t op1,vuint8m1_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll(vbool4_t mask,vuint8m2_t op1,vuint8m2_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll(vbool2_t mask,vuint8m4_t op1,vuint8m4_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll(vbool1_t mask,vuint8m8_t op1,vuint8m8_t shift,size_t \
> vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll(vbool64_t mask,vuint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll(vbool32_t mask,vuint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll(vbool16_t mask,vuint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll(vbool8_t mask,vuint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll(vbool4_t mask,vuint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll(vbool2_t mask,vuint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll(vbool64_t mask,vuint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll(vbool32_t mask,vuint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll(vbool16_t mask,vuint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll(vbool8_t mask,vuint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll(vbool4_t mask,vuint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll(vbool64_t mask,vuint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll(vbool32_t mask,vuint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll(vbool16_t mask,vuint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll(vbool8_t mask,vuint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll(mask,op1,shift,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-1.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-1.C new file mode 100644
> index 00000000000..985b32eeff0
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-2.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-2.C new file mode 100644
> index 00000000000..b98914d6705
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-3.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-3.C new file mode 100644
> index 00000000000..b366021c9c6
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_mu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_mu(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_mu(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_mu(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_mu(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_mu(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_mu(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_mu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_mu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_mu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_mu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_mu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_mu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_mu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_mu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_mu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_mu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_mu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_mu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_mu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_mu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_mu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_mu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_mu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_mu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_mu(mask,merge,op1,shift,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-1.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-1.C new file mode 100644
> index 00000000000..f050a64151b
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-2.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-2.C new file mode 100644
> index 00000000000..388ed649231
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-3.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-3.C new file mode 100644
> index 00000000000..e117f63826b
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tu(vint8mf8_t merge,vint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tu(vint8mf4_t merge,vint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tu(vint8mf2_t merge,vint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tu(vint8m1_t merge,vint8m1_t op1,vuint8m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tu(vint8m2_t merge,vint8m2_t op1,vuint8m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tu(vint8m4_t merge,vint8m4_t op1,vuint8m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tu(vint8m8_t merge,vint8m8_t op1,vuint8m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tu(vint16mf4_t merge,vint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tu(vint16mf2_t merge,vint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tu(vint16m1_t merge,vint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tu(vint16m2_t merge,vint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tu(vint16m4_t merge,vint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tu(vint16m8_t merge,vint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tu(vint32mf2_t merge,vint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tu(vint32m1_t merge,vint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tu(vint32m2_t merge,vint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tu(vint32m4_t merge,vint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tu(vint32m8_t merge,vint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tu(vint64m1_t merge,vint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tu(vint64m2_t merge,vint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tu(vint64m4_t merge,vint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tu(vint64m8_t merge,vint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tu(vuint8mf8_t merge,vuint8mf8_t op1,vuint8mf8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tu(vuint8mf4_t merge,vuint8mf4_t op1,vuint8mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tu(vuint8mf2_t merge,vuint8mf2_t op1,vuint8mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tu(vuint8m1_t merge,vuint8m1_t op1,vuint8m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tu(vuint8m2_t merge,vuint8m2_t op1,vuint8m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tu(vuint8m4_t merge,vuint8m4_t op1,vuint8m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tu(vuint8m8_t merge,vuint8m8_t op1,vuint8m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tu(vuint16mf4_t merge,vuint16mf4_t op1,vuint16mf4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tu(vuint16mf2_t merge,vuint16mf2_t op1,vuint16mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tu(vuint16m1_t merge,vuint16m1_t op1,vuint16m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tu(vuint16m2_t merge,vuint16m2_t op1,vuint16m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tu(vuint16m4_t merge,vuint16m4_t op1,vuint16m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tu(vuint16m8_t merge,vuint16m8_t op1,vuint16m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tu(vuint32mf2_t merge,vuint32mf2_t op1,vuint32mf2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tu(vuint32m1_t merge,vuint32m1_t op1,vuint32m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tu(vuint32m2_t merge,vuint32m2_t op1,vuint32m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tu(vuint32m4_t merge,vuint32m4_t op1,vuint32m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tu(vuint32m8_t merge,vuint32m8_t op1,vuint32m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tu(vuint64m1_t merge,vuint64m1_t op1,vuint64m1_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tu(vuint64m2_t merge,vuint64m2_t op1,vuint64m2_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tu(vuint64m4_t merge,vuint64m4_t op1,vuint64m4_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tu(vuint64m8_t merge,vuint64m8_t op1,vuint64m8_t \
> shift,size_t vl) +{
> +    return __riscv_vsll_tu(merge,op1,shift,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-1.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-1.C new file mode 100644
> index 00000000000..1a98a98e8b9
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-2.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-2.C new file mode 100644
> index 00000000000..ab3dfa3902c
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-3.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-3.C new file mode 100644
> index 00000000000..db3707f374e
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tum-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tum(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tum(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tum(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tum(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tum(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tum(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tum(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tum(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tum(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tum(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tum(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tum(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tum(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tum(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tum(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tum(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tum(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tum(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tum(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tum(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tum(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tum(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tum(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tum(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tum(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tum(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tum(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tum(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tum(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tum(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tum(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tum(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tum(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tum(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tum(mask,merge,op1,shift,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-1.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-1.C new file mode 100644
> index 00000000000..58aac8088ca
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-1.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-2.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-2.C new file mode 100644
> index 00000000000..164fc1ad3b6
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-2.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> diff --git a/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-3.C \
> b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-3.C new file mode 100644
> index 00000000000..d9eed7c01ee
> --- /dev/null
> +++ b/gcc/testsuite/g++.target/riscv/rvv/base/vsll_vv_tumu-3.C
> @@ -0,0 +1,292 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vint8mf8_t merge,vint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vint8mf4_t merge,vint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vint8mf2_t merge,vint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vint16mf4_t merge,vint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vint16mf2_t merge,vint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vint16m1_t merge,vint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vint32mf2_t merge,vint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vint32m1_t merge,vint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vint32m2_t merge,vint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vint64m1_t merge,vint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vint64m2_t merge,vint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vint64m4_t merge,vint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf8_t test___riscv_vsll_tumu(vbool64_t mask,vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vsll_tumu(vbool32_t mask,vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vsll_tumu(vbool16_t mask,vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vsll_tumu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vsll_tumu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vsll_tumu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vsll_tumu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vsll_tumu(vbool64_t mask,vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vsll_tumu(vbool32_t mask,vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vsll_tumu(vbool16_t mask,vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vsll_tumu(vbool8_t mask,vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vsll_tumu(vbool4_t mask,vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vsll_tumu(vbool2_t mask,vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vsll_tumu(vbool64_t mask,vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vsll_tumu(vbool32_t mask,vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vsll_tumu(vbool16_t mask,vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vsll_tumu(vbool8_t mask,vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vsll_tumu(vbool4_t mask,vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vsll_tumu(vbool64_t mask,vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vsll_tumu(vbool32_t mask,vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vsll_tumu(vbool16_t mask,vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vsll_tumu(vbool8_t mask,vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t shift,size_t vl) +{
> +    return __riscv_vsll_tumu(mask,merge,op1,shift,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
> 2 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vsll\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t\s+} \
>                 2 } } */
> --
> 2.36.3
> 


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