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List:       gcc-patches
Subject:    Re: [PATCH] RISC-V: Add vmin*.vv C API tests
From:       Kito Cheng via Gcc-patches <gcc-patches () gcc ! gnu ! org>
Date:       2023-01-31 16:48:02
Message-ID: CA+yXCZAP2RCFQwN1Gf7-adjOMNX8oz+AC48brRxLp5iwf2HN6Q () mail ! gmail ! com
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committed, thanks!

On Tue, Jan 31, 2023 at 8:27 PM <juzhe.zhong@rivai.ai> wrote:
> 
> From: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>
> 
> 
> * gcc.target/riscv/rvv/base/vmin_vv-1.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv-2.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv-3.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tu-3.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tum-1.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tum-2.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tum-3.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tumu-1.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tumu-2.c: New test.
> * gcc.target/riscv/rvv/base/vmin_vv_tumu-3.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv-1.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv-2.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv-3.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_m-1.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_m-2.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_m-3.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_mu-1.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_mu-2.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_mu-3.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tu-1.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tu-2.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tu-3.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tum-1.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tum-2.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tum-3.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tumu-1.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tumu-2.c: New test.
> * gcc.target/riscv/rvv/base/vminu_vv_tumu-3.c: New test.
> 
> ---
> .../gcc.target/riscv/rvv/base/vmin_vv-1.c     | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv-2.c     | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv-3.c     | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_m-1.c   | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_m-2.c   | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_m-3.c   | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_mu-1.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_mu-2.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_mu-3.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_tu-1.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_tu-2.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_tu-3.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_tum-1.c | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_tum-2.c | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vmin_vv_tum-3.c | 160 ++++++++++++++++++
> .../riscv/rvv/base/vmin_vv_tumu-1.c           | 160 ++++++++++++++++++
> .../riscv/rvv/base/vmin_vv_tumu-2.c           | 160 ++++++++++++++++++
> .../riscv/rvv/base/vmin_vv_tumu-3.c           | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv-1.c    | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv-2.c    | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv-3.c    | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_m-1.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_m-2.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_m-3.c  | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_mu-1.c | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_mu-2.c | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_mu-3.c | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_tu-1.c | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_tu-2.c | 160 ++++++++++++++++++
> .../gcc.target/riscv/rvv/base/vminu_vv_tu-3.c | 160 ++++++++++++++++++
> .../riscv/rvv/base/vminu_vv_tum-1.c           | 160 ++++++++++++++++++
> .../riscv/rvv/base/vminu_vv_tum-2.c           | 160 ++++++++++++++++++
> .../riscv/rvv/base/vminu_vv_tum-3.c           | 160 ++++++++++++++++++
> .../riscv/rvv/base/vminu_vv_tumu-1.c          | 160 ++++++++++++++++++
> .../riscv/rvv/base/vminu_vv_tumu-2.c          | 160 ++++++++++++++++++
> .../riscv/rvv/base/vminu_vv_tumu-3.c          | 160 ++++++++++++++++++
> 36 files changed, 5760 insertions(+)
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-3.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-1.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-2.c
> create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-3.c
> 
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-1.c new file mode 100644
> index 00000000000..147a2684211
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf8(op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf4(op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf2(op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m1(op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m2(op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m4(op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m8(op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16mf4(op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16mf2(op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m1(op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m2(op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m4(op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m8(op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32mf2(op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m1(op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m2(op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m4(op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m8(op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m1(op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m2(op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m4(op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m8(op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-2.c new file mode 100644
> index 00000000000..53c89950042
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf8(op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf4(op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf2(op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m1(op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m2(op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m4(op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m8(op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16mf4(op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16mf2(op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m1(op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m2(op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m4(op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m8(op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32mf2(op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m1(op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m2(op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m4(op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m8(op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m1(op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m2(op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m4(op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m8(op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-3.c new file mode 100644
> index 00000000000..b950023f1ba
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8(vint8mf8_t op1,vint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf8(op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4(vint8mf4_t op1,vint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf4(op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2(vint8mf2_t op1,vint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8mf2(op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1(vint8m1_t op1,vint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m1(op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2(vint8m2_t op1,vint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m2(op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4(vint8m4_t op1,vint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m4(op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8(vint8m8_t op1,vint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i8m8(op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4(vint16mf4_t op1,vint16mf4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16mf4(op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2(vint16mf2_t op1,vint16mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16mf2(op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1(vint16m1_t op1,vint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m1(op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2(vint16m2_t op1,vint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m2(op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4(vint16m4_t op1,vint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m4(op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8(vint16m8_t op1,vint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i16m8(op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2(vint32mf2_t op1,vint32mf2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32mf2(op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1(vint32m1_t op1,vint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m1(op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2(vint32m2_t op1,vint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m2(op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4(vint32m4_t op1,vint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m4(op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8(vint32m8_t op1,vint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i32m8(op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1(vint64m1_t op1,vint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m1(op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2(vint64m2_t op1,vint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m2(op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4(vint64m4_t op1,vint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m4(op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8(vint64m8_t op1,vint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vmin_vv_i64m8(op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-1.c new file mode 100644
> index 00000000000..11caa7cb3fa
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_m(vbool64_t mask,vint16mf4_t \
> op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_m(vbool32_t mask,vint16mf2_t \
> op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_m(vbool64_t mask,vint32mf2_t \
> op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-2.c new file mode 100644
> index 00000000000..95c68e93c1e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_m(vbool64_t mask,vint16mf4_t \
> op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_m(vbool32_t mask,vint16mf2_t \
> op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_m(vbool64_t mask,vint32mf2_t \
> op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_m(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-3.c new file mode 100644
> index 00000000000..dfb6d26a116
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_m-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_m(vbool64_t mask,vint8mf8_t op1,vint8mf8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_m(vbool32_t mask,vint8mf4_t op1,vint8mf4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_m(vbool16_t mask,vint8mf2_t op1,vint8mf2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_m(vbool8_t mask,vint8m1_t op1,vint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_m(vbool4_t mask,vint8m2_t op1,vint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_m(vbool2_t mask,vint8m4_t op1,vint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_m(vbool1_t mask,vint8m8_t op1,vint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_m(vbool64_t mask,vint16mf4_t \
> op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_m(vbool32_t mask,vint16mf2_t \
> op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_m(vbool16_t mask,vint16m1_t op1,vint16m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_m(vbool8_t mask,vint16m2_t op1,vint16m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_m(vbool4_t mask,vint16m4_t op1,vint16m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_m(vbool2_t mask,vint16m8_t op1,vint16m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_m(vbool64_t mask,vint32mf2_t \
> op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_m(vbool32_t mask,vint32m1_t op1,vint32m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_m(vbool16_t mask,vint32m2_t op1,vint32m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_m(vbool8_t mask,vint32m4_t op1,vint32m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_m(vbool4_t mask,vint32m8_t op1,vint32m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_m(vbool64_t mask,vint64m1_t op1,vint64m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_m(vbool32_t mask,vint64m2_t op1,vint64m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_m(vbool16_t mask,vint64m4_t op1,vint64m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_m(vbool8_t mask,vint64m8_t op1,vint64m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_m(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-1.c new file mode 100644
> index 00000000000..0c5669e7a95
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_mu(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_mu(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_mu(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_mu(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_mu(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_mu(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-2.c new file mode 100644
> index 00000000000..ede60cb31df
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_mu(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_mu(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_mu(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_mu(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_mu(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_mu(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-3.c new file mode 100644
> index 00000000000..d54732d283e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_mu-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_mu(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_mu(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_mu(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_mu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_mu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_mu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_mu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_mu(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_mu(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_mu(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_mu(vbool8_t mask,vint16m2_t merge,vint16m2_t \
> op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_mu(vbool4_t mask,vint16m4_t merge,vint16m4_t \
> op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_mu(vbool2_t mask,vint16m8_t merge,vint16m8_t \
> op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_mu(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_mu(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_mu(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_mu(vbool8_t mask,vint32m4_t merge,vint32m4_t \
> op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_mu(vbool4_t mask,vint32m8_t merge,vint32m8_t \
> op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_mu(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_mu(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_mu(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_mu(vbool8_t mask,vint64m8_t merge,vint64m8_t \
> op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-1.c new file mode 100644
> index 00000000000..2cca91133d5
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t \
> op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t \
> op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t \
> op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t \
> op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t \
> op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tu(vint16m1_t merge,vint16m1_t \
> op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tu(vint16m2_t merge,vint16m2_t \
> op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tu(vint16m4_t merge,vint16m4_t \
> op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tu(vint16m8_t merge,vint16m8_t \
> op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t \
> op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tu(vint32m1_t merge,vint32m1_t \
> op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tu(vint32m2_t merge,vint32m2_t \
> op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tu(vint32m4_t merge,vint32m4_t \
> op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tu(vint32m8_t merge,vint32m8_t \
> op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tu(vint64m1_t merge,vint64m1_t \
> op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tu(vint64m2_t merge,vint64m2_t \
> op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tu(vint64m4_t merge,vint64m4_t \
> op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tu(vint64m8_t merge,vint64m8_t \
> op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-2.c new file mode 100644
> index 00000000000..a46ccc3dd5f
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t \
> op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t \
> op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t \
> op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t \
> op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t \
> op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tu(vint16m1_t merge,vint16m1_t \
> op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tu(vint16m2_t merge,vint16m2_t \
> op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tu(vint16m4_t merge,vint16m4_t \
> op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tu(vint16m8_t merge,vint16m8_t \
> op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t \
> op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tu(vint32m1_t merge,vint32m1_t \
> op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tu(vint32m2_t merge,vint32m2_t \
> op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tu(vint32m4_t merge,vint32m4_t \
> op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tu(vint32m8_t merge,vint32m8_t \
> op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tu(vint64m1_t merge,vint64m1_t \
> op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tu(vint64m2_t merge,vint64m2_t \
> op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tu(vint64m4_t merge,vint64m4_t \
> op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tu(vint64m8_t merge,vint64m8_t \
> op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-3.c new file mode 100644
> index 00000000000..280b25eb234
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tu-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tu(vint8mf8_t merge,vint8mf8_t \
> op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tu(vint8mf4_t merge,vint8mf4_t \
> op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tu(vint8mf2_t merge,vint8mf2_t \
> op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tu(vint8m1_t merge,vint8m1_t op1,vint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tu(vint8m2_t merge,vint8m2_t op1,vint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tu(vint8m4_t merge,vint8m4_t op1,vint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tu(vint8m8_t merge,vint8m8_t op1,vint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tu(vint16mf4_t merge,vint16mf4_t \
> op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tu(vint16mf2_t merge,vint16mf2_t \
> op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tu(vint16m1_t merge,vint16m1_t \
> op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tu(vint16m2_t merge,vint16m2_t \
> op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tu(vint16m4_t merge,vint16m4_t \
> op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tu(vint16m8_t merge,vint16m8_t \
> op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tu(vint32mf2_t merge,vint32mf2_t \
> op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tu(vint32m1_t merge,vint32m1_t \
> op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tu(vint32m2_t merge,vint32m2_t \
> op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tu(vint32m4_t merge,vint32m4_t \
> op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tu(vint32m8_t merge,vint32m8_t \
> op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tu(vint64m1_t merge,vint64m1_t \
> op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tu(vint64m2_t merge,vint64m2_t \
> op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tu(vint64m4_t merge,vint64m4_t \
> op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tu(vint64m8_t merge,vint64m8_t \
> op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-1.c new file mode 100644
> index 00000000000..4204b1d4735
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tum(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tum(vbool8_t mask,vint16m2_t \
> merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tum(vbool4_t mask,vint16m4_t \
> merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tum(vbool2_t mask,vint16m8_t \
> merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tum(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tum(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tum(vbool8_t mask,vint32m4_t \
> merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tum(vbool4_t mask,vint32m8_t \
> merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tum(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tum(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tum(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tum(vbool8_t mask,vint64m8_t \
> merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-2.c new file mode 100644
> index 00000000000..cb0e97a3942
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tum(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tum(vbool8_t mask,vint16m2_t \
> merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tum(vbool4_t mask,vint16m4_t \
> merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tum(vbool2_t mask,vint16m8_t \
> merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tum(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tum(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tum(vbool8_t mask,vint32m4_t \
> merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tum(vbool4_t mask,vint32m8_t \
> merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tum(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tum(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tum(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tum(vbool8_t mask,vint64m8_t \
> merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-3.c new file mode 100644
> index 00000000000..463df447b98
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tum-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tum(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tum(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tum(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tum(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tum(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tum(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tum(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tum(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tum(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tum(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tum(vbool8_t mask,vint16m2_t \
> merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tum(vbool4_t mask,vint16m4_t \
> merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tum(vbool2_t mask,vint16m8_t \
> merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tum(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tum(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tum(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tum(vbool8_t mask,vint32m4_t \
> merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tum(vbool4_t mask,vint32m8_t \
> merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tum(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tum(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tum(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tum(vbool8_t mask,vint64m8_t \
> merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-1.c new file mode 100644
> index 00000000000..c1c76fd26e4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tumu(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tumu(vbool8_t mask,vint16m2_t \
> merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tumu(vbool4_t mask,vint16m4_t \
> merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tumu(vbool2_t mask,vint16m8_t \
> merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tumu(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tumu(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tumu(vbool8_t mask,vint32m4_t \
> merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tumu(vbool4_t mask,vint32m8_t \
> merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tumu(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tumu(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tumu(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tumu(vbool8_t mask,vint64m8_t \
> merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-2.c new file mode 100644
> index 00000000000..e233686ad56
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tumu(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tumu(vbool8_t mask,vint16m2_t \
> merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tumu(vbool4_t mask,vint16m4_t \
> merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tumu(vbool2_t mask,vint16m8_t \
> merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tumu(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tumu(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tumu(vbool8_t mask,vint32m4_t \
> merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tumu(vbool4_t mask,vint32m8_t \
> merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tumu(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tumu(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tumu(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tumu(vbool8_t mask,vint64m8_t \
> merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-3.c new file mode 100644
> index 00000000000..a45ee62ca32
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vmin_vv_tumu-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vint8mf8_t test___riscv_vmin_vv_i8mf8_tumu(vbool64_t mask,vint8mf8_t \
> merge,vint8mf8_t op1,vint8mf8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf4_t test___riscv_vmin_vv_i8mf4_tumu(vbool32_t mask,vint8mf4_t \
> merge,vint8mf4_t op1,vint8mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8mf2_t test___riscv_vmin_vv_i8mf2_tumu(vbool16_t mask,vint8mf2_t \
> merge,vint8mf2_t op1,vint8mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m1_t test___riscv_vmin_vv_i8m1_tumu(vbool8_t mask,vint8m1_t merge,vint8m1_t \
> op1,vint8m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m2_t test___riscv_vmin_vv_i8m2_tumu(vbool4_t mask,vint8m2_t merge,vint8m2_t \
> op1,vint8m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m4_t test___riscv_vmin_vv_i8m4_tumu(vbool2_t mask,vint8m4_t merge,vint8m4_t \
> op1,vint8m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint8m8_t test___riscv_vmin_vv_i8m8_tumu(vbool1_t mask,vint8m8_t merge,vint8m8_t \
> op1,vint8m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i8m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf4_t test___riscv_vmin_vv_i16mf4_tumu(vbool64_t mask,vint16mf4_t \
> merge,vint16mf4_t op1,vint16mf4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16mf2_t test___riscv_vmin_vv_i16mf2_tumu(vbool32_t mask,vint16mf2_t \
> merge,vint16mf2_t op1,vint16mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m1_t test___riscv_vmin_vv_i16m1_tumu(vbool16_t mask,vint16m1_t \
> merge,vint16m1_t op1,vint16m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m2_t test___riscv_vmin_vv_i16m2_tumu(vbool8_t mask,vint16m2_t \
> merge,vint16m2_t op1,vint16m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m4_t test___riscv_vmin_vv_i16m4_tumu(vbool4_t mask,vint16m4_t \
> merge,vint16m4_t op1,vint16m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint16m8_t test___riscv_vmin_vv_i16m8_tumu(vbool2_t mask,vint16m8_t \
> merge,vint16m8_t op1,vint16m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i16m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32mf2_t test___riscv_vmin_vv_i32mf2_tumu(vbool64_t mask,vint32mf2_t \
> merge,vint32mf2_t op1,vint32mf2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m1_t test___riscv_vmin_vv_i32m1_tumu(vbool32_t mask,vint32m1_t \
> merge,vint32m1_t op1,vint32m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m2_t test___riscv_vmin_vv_i32m2_tumu(vbool16_t mask,vint32m2_t \
> merge,vint32m2_t op1,vint32m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m4_t test___riscv_vmin_vv_i32m4_tumu(vbool8_t mask,vint32m4_t \
> merge,vint32m4_t op1,vint32m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint32m8_t test___riscv_vmin_vv_i32m8_tumu(vbool4_t mask,vint32m8_t \
> merge,vint32m8_t op1,vint32m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i32m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m1_t test___riscv_vmin_vv_i64m1_tumu(vbool64_t mask,vint64m1_t \
> merge,vint64m1_t op1,vint64m1_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m2_t test___riscv_vmin_vv_i64m2_tumu(vbool32_t mask,vint64m2_t \
> merge,vint64m2_t op1,vint64m2_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m4_t test___riscv_vmin_vv_i64m4_tumu(vbool16_t mask,vint64m4_t \
> merge,vint64m4_t op1,vint64m4_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vint64m8_t test___riscv_vmin_vv_i64m8_tumu(vbool8_t mask,vint64m8_t \
> merge,vint64m8_t op1,vint64m8_t op2,size_t vl) +{
> +    return __riscv_vmin_vv_i64m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vmin\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-1.c new file mode 100644
> index 00000000000..9244a4fe6d7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf8(op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf4(op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf2(op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m1(op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m2(op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m4(op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m8(op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u16mf4(op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u16mf2(op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m1(op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m2(op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m4(op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m8(op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u32mf2(op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m1(op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m2(op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m4(op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m8(op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m1(op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m2(op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m4(op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m8(op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-2.c new file mode 100644
> index 00000000000..f5329db672d
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf8(op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf4(op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf2(op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m1(op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m2(op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m4(op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m8(op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u16mf4(op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u16mf2(op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m1(op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m2(op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m4(op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m8(op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u32mf2(op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m1(op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m2(op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m4(op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m8(op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m1(op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m2(op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m4(op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m8(op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-3.c new file mode 100644
> index 00000000000..cfc2115894a
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8(vuint8mf8_t op1,vuint8mf8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf8(op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4(vuint8mf4_t op1,vuint8mf4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf4(op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2(vuint8mf2_t op1,vuint8mf2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8mf2(op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1(vuint8m1_t op1,vuint8m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m1(op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2(vuint8m2_t op1,vuint8m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m2(op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4(vuint8m4_t op1,vuint8m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m4(op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8(vuint8m8_t op1,vuint8m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u8m8(op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4(vuint16mf4_t op1,vuint16mf4_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u16mf4(op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2(vuint16mf2_t op1,vuint16mf2_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u16mf2(op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1(vuint16m1_t op1,vuint16m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m1(op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2(vuint16m2_t op1,vuint16m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m2(op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4(vuint16m4_t op1,vuint16m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m4(op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8(vuint16m8_t op1,vuint16m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u16m8(op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2(vuint32mf2_t op1,vuint32mf2_t op2,size_t \
> vl) +{
> +    return __riscv_vminu_vv_u32mf2(op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1(vuint32m1_t op1,vuint32m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m1(op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2(vuint32m2_t op1,vuint32m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m2(op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4(vuint32m4_t op1,vuint32m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m4(op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8(vuint32m8_t op1,vuint32m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u32m8(op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1(vuint64m1_t op1,vuint64m1_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m1(op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2(vuint64m2_t op1,vuint64m2_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m2(op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4(vuint64m4_t op1,vuint64m4_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m4(op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8(vuint64m8_t op1,vuint64m8_t op2,size_t vl)
> +{
> +    return __riscv_vminu_vv_u64m8(op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-1.c new file mode 100644
> index 00000000000..efff408cf61
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t \
> op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t \
> op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t \
> op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t \
> op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t \
> op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_m(vbool16_t mask,vuint16m1_t \
> op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_m(vbool8_t mask,vuint16m2_t \
> op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_m(vbool4_t mask,vuint16m4_t \
> op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_m(vbool2_t mask,vuint16m8_t \
> op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t \
> op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_m(vbool32_t mask,vuint32m1_t \
> op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_m(vbool16_t mask,vuint32m2_t \
> op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_m(vbool8_t mask,vuint32m4_t \
> op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_m(vbool4_t mask,vuint32m8_t \
> op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_m(vbool64_t mask,vuint64m1_t \
> op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_m(vbool32_t mask,vuint64m2_t \
> op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_m(vbool16_t mask,vuint64m4_t \
> op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_m(mask,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_m(vbool8_t mask,vuint64m8_t \
> op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_m(mask,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-2.c new file mode 100644
> index 00000000000..7f624e3466c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t \
> op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t \
> op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t \
> op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t \
> op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t \
> op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_m(vbool16_t mask,vuint16m1_t \
> op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_m(vbool8_t mask,vuint16m2_t \
> op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_m(vbool4_t mask,vuint16m4_t \
> op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_m(vbool2_t mask,vuint16m8_t \
> op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t \
> op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_m(vbool32_t mask,vuint32m1_t \
> op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_m(vbool16_t mask,vuint32m2_t \
> op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_m(vbool8_t mask,vuint32m4_t \
> op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_m(vbool4_t mask,vuint32m8_t \
> op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_m(vbool64_t mask,vuint64m1_t \
> op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_m(vbool32_t mask,vuint64m2_t \
> op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_m(vbool16_t mask,vuint64m4_t \
> op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_m(mask,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_m(vbool8_t mask,vuint64m8_t \
> op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_m(mask,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-3.c new file mode 100644
> index 00000000000..4e0e2c5bfe4
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_m-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_m(vbool64_t mask,vuint8mf8_t \
> op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_m(vbool32_t mask,vuint8mf4_t \
> op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_m(vbool16_t mask,vuint8mf2_t \
> op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_m(vbool8_t mask,vuint8m1_t op1,vuint8m1_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_m(vbool4_t mask,vuint8m2_t op1,vuint8m2_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_m(vbool2_t mask,vuint8m4_t op1,vuint8m4_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_m(vbool1_t mask,vuint8m8_t op1,vuint8m8_t \
> op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_m(vbool64_t mask,vuint16mf4_t \
> op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_m(vbool32_t mask,vuint16mf2_t \
> op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_m(vbool16_t mask,vuint16m1_t \
> op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_m(vbool8_t mask,vuint16m2_t \
> op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_m(vbool4_t mask,vuint16m4_t \
> op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_m(vbool2_t mask,vuint16m8_t \
> op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_m(vbool64_t mask,vuint32mf2_t \
> op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_m(vbool32_t mask,vuint32m1_t \
> op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_m(vbool16_t mask,vuint32m2_t \
> op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_m(vbool8_t mask,vuint32m4_t \
> op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_m(vbool4_t mask,vuint32m8_t \
> op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_m(vbool64_t mask,vuint64m1_t \
> op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_m(vbool32_t mask,vuint64m2_t \
> op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_m(vbool16_t mask,vuint64m4_t \
> op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_m(mask,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_m(vbool8_t mask,vuint64m8_t \
> op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_m(mask,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-1.c new file mode 100644
> index 00000000000..d6fef144ab3
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_mu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-2.c new file mode 100644
> index 00000000000..c8868745e3b
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_mu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-3.c new file mode 100644
> index 00000000000..5daa8ee4dac
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_mu-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_mu(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_mu(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_mu(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_mu(vbool8_t mask,vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_mu(vbool4_t mask,vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_mu(vbool2_t mask,vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_mu(vbool1_t mask,vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_mu(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_mu(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_mu(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_mu(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_mu(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_mu(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_mu(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_mu(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_mu(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_mu(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_mu(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_mu(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_mu(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_mu(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_mu(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_mu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*t[au],\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-1.c new file mode 100644
> index 00000000000..c40e32d9667
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tu(merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tu(merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-2.c new file mode 100644
> index 00000000000..f6d41c3bc8e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tu(merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tu(merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-3.c new file mode 100644
> index 00000000000..d44017d530c
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tu-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tu(vuint8mf8_t merge,vuint8mf8_t \
> op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tu(vuint8mf4_t merge,vuint8mf4_t \
> op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tu(vuint8mf2_t merge,vuint8mf2_t \
> op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tu(vuint8m1_t merge,vuint8m1_t \
> op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tu(vuint8m2_t merge,vuint8m2_t \
> op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tu(vuint8m4_t merge,vuint8m4_t \
> op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tu(vuint8m8_t merge,vuint8m8_t \
> op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tu(vuint16mf4_t merge,vuint16mf4_t \
> op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tu(vuint16mf2_t merge,vuint16mf2_t \
> op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tu(vuint16m1_t merge,vuint16m1_t \
> op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tu(vuint16m2_t merge,vuint16m2_t \
> op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tu(vuint16m4_t merge,vuint16m4_t \
> op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tu(vuint16m8_t merge,vuint16m8_t \
> op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tu(vuint32mf2_t merge,vuint32mf2_t \
> op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tu(vuint32m1_t merge,vuint32m1_t \
> op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tu(vuint32m2_t merge,vuint32m2_t \
> op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tu(vuint32m4_t merge,vuint32m4_t \
> op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tu(vuint32m8_t merge,vuint32m8_t \
> op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tu(vuint64m1_t merge,vuint64m1_t \
> op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tu(vuint64m2_t merge,vuint64m2_t \
> op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tu(vuint64m4_t merge,vuint64m4_t \
> op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tu(merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tu(vuint64m8_t merge,vuint64m8_t \
> op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tu(merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-1.c new file mode 100644
> index 00000000000..e5c5cd48367
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tum(vbool8_t mask,vuint8m1_t \
> merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tum(vbool4_t mask,vuint8m2_t \
> merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tum(vbool2_t mask,vuint8m4_t \
> merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tum(vbool1_t mask,vuint8m8_t \
> merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tum(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-2.c new file mode 100644
> index 00000000000..69c75e8bed7
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tum(vbool8_t mask,vuint8m1_t \
> merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tum(vbool4_t mask,vuint8m2_t \
> merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tum(vbool2_t mask,vuint8m4_t \
> merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tum(vbool1_t mask,vuint8m8_t \
> merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tum(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-3.c new file mode 100644
> index 00000000000..a1bada97477
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tum-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tum(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tum(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tum(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tum(vbool8_t mask,vuint8m1_t \
> merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tum(vbool4_t mask,vuint8m2_t \
> merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tum(vbool2_t mask,vuint8m4_t \
> merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tum(vbool1_t mask,vuint8m8_t \
> merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tum(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tum(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tum(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tum(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tum(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tum(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tum(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tum(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tum(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tum(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tum(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tum(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tum(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tum(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tum(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tum(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*m[au]\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-1.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-1.c new file mode 100644
> index 00000000000..a77581db309
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-1.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t \
> merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t \
> merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t \
> merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t \
> merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tumu(mask,merge,op1,op2,vl);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-2.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-2.c new file mode 100644
> index 00000000000..ba2ff9b5af9
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-2.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t \
> merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t \
> merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t \
> merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t \
> merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tumu(mask,merge,op1,op2,31);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e8,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e16,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e32,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetivli\s+zero,\s*31,\s*e64,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> diff --git a/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-3.c \
> b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-3.c new file mode 100644
> index 00000000000..8cbf11bc10e
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/riscv/rvv/base/vminu_vv_tumu-3.c
> @@ -0,0 +1,160 @@
> +/* { dg-do compile } */
> +/* { dg-options "-march=rv32gcv -mabi=ilp32d -O3 -fno-schedule-insns \
> -fno-schedule-insns2" } */ +
> +#include "riscv_vector.h"
> +
> +vuint8mf8_t test___riscv_vminu_vv_u8mf8_tumu(vbool64_t mask,vuint8mf8_t \
> merge,vuint8mf8_t op1,vuint8mf8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf4_t test___riscv_vminu_vv_u8mf4_tumu(vbool32_t mask,vuint8mf4_t \
> merge,vuint8mf4_t op1,vuint8mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8mf2_t test___riscv_vminu_vv_u8mf2_tumu(vbool16_t mask,vuint8mf2_t \
> merge,vuint8mf2_t op1,vuint8mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m1_t test___riscv_vminu_vv_u8m1_tumu(vbool8_t mask,vuint8m1_t \
> merge,vuint8m1_t op1,vuint8m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m2_t test___riscv_vminu_vv_u8m2_tumu(vbool4_t mask,vuint8m2_t \
> merge,vuint8m2_t op1,vuint8m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m4_t test___riscv_vminu_vv_u8m4_tumu(vbool2_t mask,vuint8m4_t \
> merge,vuint8m4_t op1,vuint8m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint8m8_t test___riscv_vminu_vv_u8m8_tumu(vbool1_t mask,vuint8m8_t \
> merge,vuint8m8_t op1,vuint8m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u8m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf4_t test___riscv_vminu_vv_u16mf4_tumu(vbool64_t mask,vuint16mf4_t \
> merge,vuint16mf4_t op1,vuint16mf4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16mf2_t test___riscv_vminu_vv_u16mf2_tumu(vbool32_t mask,vuint16mf2_t \
> merge,vuint16mf2_t op1,vuint16mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m1_t test___riscv_vminu_vv_u16m1_tumu(vbool16_t mask,vuint16m1_t \
> merge,vuint16m1_t op1,vuint16m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m2_t test___riscv_vminu_vv_u16m2_tumu(vbool8_t mask,vuint16m2_t \
> merge,vuint16m2_t op1,vuint16m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m4_t test___riscv_vminu_vv_u16m4_tumu(vbool4_t mask,vuint16m4_t \
> merge,vuint16m4_t op1,vuint16m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint16m8_t test___riscv_vminu_vv_u16m8_tumu(vbool2_t mask,vuint16m8_t \
> merge,vuint16m8_t op1,vuint16m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u16m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32mf2_t test___riscv_vminu_vv_u32mf2_tumu(vbool64_t mask,vuint32mf2_t \
> merge,vuint32mf2_t op1,vuint32mf2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32mf2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m1_t test___riscv_vminu_vv_u32m1_tumu(vbool32_t mask,vuint32m1_t \
> merge,vuint32m1_t op1,vuint32m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m2_t test___riscv_vminu_vv_u32m2_tumu(vbool16_t mask,vuint32m2_t \
> merge,vuint32m2_t op1,vuint32m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m4_t test___riscv_vminu_vv_u32m4_tumu(vbool8_t mask,vuint32m4_t \
> merge,vuint32m4_t op1,vuint32m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint32m8_t test___riscv_vminu_vv_u32m8_tumu(vbool4_t mask,vuint32m8_t \
> merge,vuint32m8_t op1,vuint32m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u32m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m1_t test___riscv_vminu_vv_u64m1_tumu(vbool64_t mask,vuint64m1_t \
> merge,vuint64m1_t op1,vuint64m1_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m1_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m2_t test___riscv_vminu_vv_u64m2_tumu(vbool32_t mask,vuint64m2_t \
> merge,vuint64m2_t op1,vuint64m2_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m2_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m4_t test___riscv_vminu_vv_u64m4_tumu(vbool16_t mask,vuint64m4_t \
> merge,vuint64m4_t op1,vuint64m4_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m4_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +vuint64m8_t test___riscv_vminu_vv_u64m8_tumu(vbool8_t mask,vuint64m8_t \
> merge,vuint64m8_t op1,vuint64m8_t op2,size_t vl) +{
> +    return __riscv_vminu_vv_u64m8_tumu(mask,merge,op1,op2,32);
> +}
> +
> +
> +
> +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e8,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e16,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*mf2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e32,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m1,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m2,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m4,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
> 1 } } */ +/* { dg-final { scan-assembler-times \
> {vsetvli\s+zero,\s*[a-x0-9]+,\s*e64,\s*m8,\s*tu,\s*mu\s+vminu\.vv\s+v[0-9]+,\s*v[0-9]+,\s*v[0-9]+,\s*v0.t} \
>                 1 } } */
> --
> 2.36.3
> 


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