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List:       gcc
Subject:    Re: Unable to build M32C gcc port
From:       Richard Henderson <rth () redhat ! com>
Date:       2012-07-31 17:34:31
Message-ID: 50181727.8060702 () redhat ! com
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On 2012-07-31 03:47, Nick Clifton wrote:
>       if (TARGET_A24)
>         {
>           set_optab_handler (cstore_optab, QImode, CODE_FOR_cstoreqi4_24);
>           set_optab_handler (cstore_optab, HImode, CODE_FOR_cstorehi4_24);
>           set_optab_handler (cstore_optab, PSImode, CODE_FOR_cstorepsi4_24);
>         }
>     }
> 
>   But I could not see an obvious way to fix it.  Should I be using
>   swap_optab_handler as a replacement function ?

Try this.  I had a look at 

int feq(int x, int y) { return x == y; }
int fne(int x, int y) { return x != y; }
int flt(int x, int y) { return x < y; }
int fle(int x, int y) { return x <= y; }
int fgt(int x, int y) { return x > y; }
int fge(int x, int y) { return x >= y; }

and combine is able to clean up the mess for -mcpu=m32c.


r~

["z" (text/plain)]

diff --git a/gcc/config/m32c/cond.md b/gcc/config/m32c/cond.md
index c751070..7ae0c90 100644
--- a/gcc/config/m32c/cond.md
+++ b/gcc/config/m32c/cond.md
@@ -152,7 +152,27 @@
 
 ;; These are the pre-split patterns for the conditional sets.
 
-(define_insn_and_split "cstore<mode>4"
+(define_expand "cstore<mode>4"
+  [(set (match_operand:QI 0 "register_operand" "=Rqi")
+	(match_operator:QI 1 "ordered_comparison_operator"
+	 [(match_operand:QHPSI 2 "mra_operand" "RraSd")
+	  (match_operand:QHPSI 3 "mrai_operand" "RraSdi")]))]
+  ""
+{
+  if (TARGET_A16)
+    emit_insn (gen_cstore<mode>4_16 (operands[0], operands[1],
+				     operands[2], operands[3]));
+  else
+    {
+      rtx o = gen_reg_rtx (HImode);
+      emit_insn (gen_cstore<mode>4_24 (o, operands[1],
+				       operands[2], operands[3]));
+      emit_move_insn (operands[0], gen_lowpart (QImode, o));
+    }
+  DONE;
+})
+
+(define_insn_and_split "cstore<mode>4_16"
   [(set (match_operand:QI 0 "register_operand" "=Rqi")
 	(match_operator:QI 1 "ordered_comparison_operator"
 	 [(match_operand:QHPSI 2 "mra_operand" "RraSd")
diff --git a/gcc/config/m32c/m32c.c b/gcc/config/m32c/m32c.c
index 79b03fa..878be09 100644
--- a/gcc/config/m32c/m32c.c
+++ b/gcc/config/m32c/m32c.c
@@ -1857,25 +1857,6 @@ m32c_trampoline_init (rtx m_tramp, tree fndecl, rtx chainval)
 #undef A0
 }
 
-/* Implicit Calls to Library Routines */
-
-#undef TARGET_INIT_LIBFUNCS
-#define TARGET_INIT_LIBFUNCS m32c_init_libfuncs
-static void
-m32c_init_libfuncs (void)
-{
-  /* We do this because the M32C has an HImode operand, but the
-     M16C has an 8-bit operand.  Since gcc looks at the match data
-     and not the expanded rtl, we have to reset the optab so that
-     the right modes are found. */
-  if (TARGET_A24)
-    {
-      set_optab_handler (cstore_optab, QImode, CODE_FOR_cstoreqi4_24);
-      set_optab_handler (cstore_optab, HImode, CODE_FOR_cstorehi4_24);
-      set_optab_handler (cstore_optab, PSImode, CODE_FOR_cstorepsi4_24);
-    }
-}
-
 /* Addressing Modes */
 
 /* The r8c/m32c family supports a wide range of non-orthogonal


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