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List: full-disclosure
Subject: Re: [Full-disclosure] Intel Core 2 CPUs are buggy. Patch your cpus
From: "James Matthews" <nytrokiss () gmail ! com>
Date: 2007-06-28 19:42:43
Message-ID: 8a6b8e350706281242p6f915ebbnfbd3047649696672 () mail ! gmail ! com
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It's scary that these things cannot be patched. And this post will probably
result in intel taking down that document saying look now there are now no
holes!!!!
On 6/28/07, Peter Ferrie <pferrie@symantec.com> wrote:
>
> > - Basically the MMU simply does not operate as specified/implimented
> > in previous generations of x86 hardware. It is not just buggy, but
> > Intel has gone further and defined "new ways to handle page tables"
> > (see page 58).
>
> I'm not sure about this - I understood it to mean that if you touch a
> table, you have to invalidate the TLB that corresponds to its linear
> address. This was always how Intel CPUs behaved, even the old ones.
> What changed?
>
> > - Some of these bugs are along the lines of "buffer overflow"; where
> > a write-protect or non-execute bit for a page table entry is
> ignored.
>
> Same thing here - altering tables without flushing the TLBs will result in
> cached data being used instead. Intel is documenting it very well now,
> but
> it's not new behaviour.
>
> > Others are floating point instruction non-coherencies, or memory
> > corruptions -- outside of the range of permitted writing for the
> > process -- running common instruction sequences.
>
> The FPU memory corruption is old behaviour, too.
>
> Certainly, there are some scary things in the list, but many of them are
> behaviours that are being documented for the first time, yet they exist
> in CPUs since even the 486, for example.
>
> _______________________________________________
> Full-Disclosure - We believe in it.
> Charter: http://lists.grok.org.uk/full-disclosure-charter.html
> Hosted and sponsored by Secunia - http://secunia.com/
>
--
http://www.goldwatches.com/watches.asp?Brand=14
http://www.jewelerslounge.com
[Attachment #5 (text/html)]
It's scary that these things cannot be patched. And this post will probably result in intel \
taking down that document saying look now there are now no holes!!!!<br><br><div><span \
class="gmail_quote">On 6/28/07, <b class="gmail_sendername"> Peter Ferrie</b> <<a \
href="mailto:pferrie@symantec.com">pferrie@symantec.com</a>> wrote:</span><blockquote \
class="gmail_quote" style="border-left: 1px solid rgb(204, 204, 204); margin: 0pt 0pt 0pt \
0.8ex; padding-left: 1ex;"> > - Basically the MMU simply does not operate as \
specified/implimented<br>> in previous generations of x86 \
hardware. It is not just buggy, but<br>> Intel has gone \
further and defined "new ways to handle page tables" <br>> \
(see page 58).<br><br>I'm not sure about this - I understood it to mean that if you touch \
a<br>table, you have to invalidate the TLB that corresponds to its \
linear<br>address. This was always how Intel CPUs behaved, even the old ones. \
<br>What changed?<br><br>> - Some of these bugs are along the lines of \
"buffer overflow"; where<br>> a write-protect or \
non-execute bit for a page table entry is ignored.<br><br>Same thing here - altering tables \
without flushing the TLBs will result in <br>cached data being used instead. Intel \
is documenting it very well now, but<br>it's not new \
behaviour.<br><br>> Others are floating point instruction \
non-coherencies, or memory<br>> corruptions -- outside of the range \
of permitted writing for the <br>> process -- running common \
instruction sequences.<br><br>The FPU memory corruption is old behaviour, \
too.<br><br>Certainly, there are some scary things in the list, but many of them \
are<br>behaviours that are being documented for the first time, yet they exist <br>in CPUs \
since even the 486, for \
example.<br><br>_______________________________________________<br>Full-Disclosure - We believe \
in it.<br>Charter: <a \
href="http://lists.grok.org.uk/full-disclosure-charter.html">http://lists.grok.org.uk/full-disclosure-charter.html
</a><br>Hosted and sponsored by Secunia - <a \
href="http://secunia.com/">http://secunia.com/</a><br></blockquote></div><br><br \
clear="all"><br>-- <br><a \
href="http://www.goldwatches.com/watches.asp?Brand=14">http://www.goldwatches.com/watches.asp?Brand=14
</a><br><a href="http://www.jewelerslounge.com">http://www.jewelerslounge.com</a>
_______________________________________________
Full-Disclosure - We believe in it.
Charter: http://lists.grok.org.uk/full-disclosure-charter.html
Hosted and sponsored by Secunia - http://secunia.com/
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