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List:       freedesktop-xorg
Subject:    Re: [PATCH/RFC] Add Widescreen Signalling to intel driver
From:       elupus <elupus () ecce ! se>
Date:       2008-05-31 19:45:25
Message-ID: eik6yder6orp$.1pdqrwnckt1g3$.dlg () 40tude ! net
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On Sat, 31 May 2008 21:44:22 +0200, elupus wrote:

> Hi, 
> 
> I'm playing around with wss switching in the intel driver. According to
> docs it should be supported. This is what I have so far, I assume the
> signal sent should be based on resolution, and only sent when in SD modes.
> But i'd like to get it working first :).
> 
> This patch doesn't seem to work at the moment. I think it could be partly
> due to this comment that's in intel docs 
> 
> "IMPORTANT: Since WSS uses line 23 to transmit data, the active region has
> to be downsized by two lines and the vertical blanking has to be increased
> by two lines."
> 
> Any ideas on how to fix that?
> 
> Regards
> Joakim

sigh.. Maybe should supply patch.

Joakim
["wss.patch" (text/x-patch)]

diff --git a/src/i810_reg.h b/src/i810_reg.h
index d1fed22..90077ac 100644
--- a/src/i810_reg.h
+++ b/src/i810_reg.h
@@ -1957,6 +1957,55 @@ SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 #define TV_V_CHROMA_42		0x684a8
 /** @} */
 
+
+/** @defgroup TV_WSS_CONTROL
+ * @{
+ */
+#define TV_WSS_CONTROL		0x680B0
+# define TV_WSS_ENABLE			(1 << 31)
+/**
+ * Specifies which field to send the WSS data in.
+ *
+ * WSS data is usually sent in field 0.
+ */
+# define TV_WSS_FID_MASK		(1 << 30)
+# define TV_WSS_FID_SHIFT		30
+/** Sets the horizontal position of the WSS data.  Usually 148. */
+# define TV_WSS_HOFF_MASK		0x03ff0000
+# define TV_WSS_HOFF_SHIFT		16
+/** Sets the clock divider for WSS clock Usually 27 for 5MHz bit clock */
+# define TV_WSS_BIT_MASK		0x00007f00
+# define TV_WSS_BIT_SHIFT		8
+/** 
+ * Sets the line number to display the WSS data minus 1.
+ * Usually 25 to be displayed on line 23
+ */
+# define TV_WSS_LINE_MASK		0x0000001f
+# define TV_WSS_LINE_SHIFT		0
+
+/** @} */
+
+/** @defgroup TV_WSS_DATA
+ * @{
+ */
+#define TV_WSS_DATA			0x680B4
+
+# define TV_WSS_DATA_ASPECT_MASK	0x0000000f
+# define TV_WSS_DATA_ASPECT_SHIFT	0
+
+# define TV_WSS_DATA_SERV_MASK		0x000000f0
+# define TV_WSS_DATA_SERV_SHIFT		4
+
+# define TV_WSS_DATA_SUB_MASK		0x00000700
+# define TV_WSS_DATA_SUB_SHIFT		8
+
+# define TV_WSS_DATA_OTHER_MASK		0x00003800
+# define TV_WSS_DATA_OTHER_SHIFT	11
+
+/** @}
+ */
+
+
 #define PIPEA_DSL		0x70000
 
 #define PIPEACONF 0x70008
diff --git a/src/i830_tv.c b/src/i830_tv.c
index f037171..3f1b463 100644
--- a/src/i830_tv.c
+++ b/src/i830_tv.c
@@ -1235,6 +1235,20 @@ i830_tv_mode_set(xf86OutputPtr output, DisplayModePtr mode,
 	OUTREG(TV_V_LUMA_0 + (i<<2), tv_mode->filter_table[j++]);
     for (i = 0; i < 43; i++)
 	OUTREG(TV_V_CHROMA_0 + (i<<2), tv_mode->filter_table[j++]);
+
+
+
+    wssctl  = TV_WSS_ENABLE;
+    wssctl |= 1 << TV_WSS_FID_SHIFT;
+    wssctl |= 148 << TV_WSS_HOFF_SHIFT;
+    wssctl |= 27 << TV_WSS_BIT_SHIFT;
+    wssctl |= 25 << TV_WSS_LINE_SHIFT;
+
+    wssdata = 0x7;
+
+    OUTREG(TV_WSS_DATA, wssdata);
+    OUTREG(TV_WSS_CONTROL, wssctl);
+
     OUTREG(TV_DAC, 0);
     OUTREG(TV_CTL, tv_ctl);
 }

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