[prev in list] [next in list] [prev in thread] [next in thread]
List: freedesktop-intel-gfx
Subject: [Intel-gfx] [PATCH 3/6] drm/i915/skl: Expose DC5/DC6 entry counts
From: damien.lespiau () intel ! com (Damien Lespiau)
Date: 2015-06-30 18:28:56
Message-ID: 1435688939-26523-4-git-send-email-damien.lespiau () intel ! com
[Download RAW message or body]
The CSR firmware expose two counters, handy to check if we are indeed
entering DC5/DC6.
Signed-off-by: Damien Lespiau <damien.lespiau at intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 7 +++++++
drivers/gpu/drm/i915/i915_reg.h | 4 ++++
2 files changed, 11 insertions(+)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5dad2ac..0af19c0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -2623,6 +2623,13 @@ static int i915_dmc_info(struct seq_file *m, void *unused)
seq_printf(m, "version: %d.%d\n", CSR_VERSION_MAJOR(csr->version),
CSR_VERSION_MINOR(csr->version));
+ if (IS_SKYLAKE(dev) && csr->version >= CSR_VERSION(1, 6)) {
+ seq_printf(m, "DC3 -> DC5 count: %d\n",
+ I915_READ(SKL_CSR_DC3_DC5_COUNT));
+ seq_printf(m, "DC5 -> DC6 count: %d\n",
+ I915_READ(SKL_CSR_DC5_DC6_COUNT));
+ }
+
return 0;
}
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index ac985c5..48a398c 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -5552,6 +5552,10 @@ enum skl_disp_power_wells {
#define GAMMA_MODE_MODE_12BIT (2 << 0)
#define GAMMA_MODE_MODE_SPLIT (3 << 0)
+/* DMC/CSR */
+#define SKL_CSR_DC3_DC5_COUNT 0x80030
+#define SKL_CSR_DC5_DC6_COUNT 0x8002C
+
/* interrupts */
#define DE_MASTER_IRQ_CONTROL (1 << 31)
#define DE_SPRITEB_FLIP_DONE (1 << 29)
--
2.1.0
[prev in list] [next in list] [prev in thread] [next in thread]
Configure |
About |
News |
Add a list |
Sponsored by KoreLogic