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List:       freebsd-ppc
Subject:    Re: Fatal kernel trap on 7400 G4 processors
From:       Matt Sealey <matt () genesi-usa ! com>
Date:       2008-09-30 20:43:29
Message-ID: 48E28F71.4070906 () genesi-usa ! com
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Shouldn't be doing it on a 7447A or 7448 either as they are 744x series
which explicitly does not have L3 cache capability. Ironically these
are the only chips where you can actually determine the difference between
having L3 and not having L3, since the 7447 and 7457 (and all previous pairs)
share the same CPU PVR.

-- 
Matt Sealey <matt@genesi-usa.com>
Genesi, Manager, Developer Relations

Marco Trillo wrote:
> Hi all,
> 
> Recent 8.0-current kernels cause a "fatal kernel trap" on 7400 G4 processors:
> 
> fatal kernel trap
> 
> exception = 0x7 (program)
> srr0 = 0x5336bc
> srr1 = 0x83032
> lr = 0x5334b4
> 
> Stopped at 0x5336bc mfspr 0, dccr
> 
> The address 0x5336bc corresponds to function cpu_setup() in powerpc/cpu.c:
> 
>   5336b4:       7f 9e 00 00     cmpw    cr7,r30,r0
>   5336b8:       40 be 02 94     bne+    cr7,53394c <cpu_setup+0x5f4>
>   5336bc:       7c 1a fa a6     mfdccr  r0 <<<<< here
>   5336c0:       3d 20 00 5f     lis     r9,95
> 
> I tracked the line to the following code in cpu.c:
> 
> 	switch (vers) {
> 		case MPC7400:
> 		case MPC7410:
> 		case MPC7447A:
> 		case MPC7448:
> 		case MPC7450:
> 		case MPC7455:
> 		case MPC7457:
> 			/* G3 systems don't have an L3 cache, so only check
> 			 * for G4 and above */
> 
> 			l3cr_config = mfspr(SPR_L3CR); <<<< here
> 
> 			/* Fallthrough */
> 
> In include/spr.h I see the following:
> 
> #define	SPR_L3CR		0x3fa	/* .6. L3 Control Register */
> #define	SPR_DCCR		0x3fa	/* 4.. Data Cache Cachability Register */
> 
> So it seems that the 7400 processor doesn't have these registers so it
> causes a fault.
> 
> What do you think?
> 
> Thanks,
> Marco.
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