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List: flashrom
Subject: [flashrom] not able to successfully update my firmware
From: Wagner Rodrigo <wrmbrr () gmail ! com>
Date: 2022-08-13 23:17:49
Message-ID: CALqHrHapiJAhRDLzaXcpXz-K-O1ZjrDB5ebaOfxHU=nor+KJDA () mail ! gmail ! com
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flashrom v1.2 on Linux 5.15.58-2-lts (x86_64)
flashrom is free software, get the source code at https://flashrom.org
flashrom was built with libpci 3.8.0, GCC 12.1.0, little endian
Command line (3 args): flashrom --programmer internal -V
Using clock_gettime for delay loops (clk_id: 1, resolution: 1ns).
Initializing internal programmer
get_mtd_info: device_name: "intel-spi", is_writeable: 0, numeraseregions:
0, total_size: 8388608, erasesize: 4096
No coreboot table found.
Using Internal DMI decoder.
No DMI table found.
Found chipset "Intel Lynx Point LP Premium" with PCI ID 8086:9c43.
This chipset is marked as untested. If you are using an up-to-date version
of flashrom *and* were (not) able to successfully update your firmware with
it,
then please email a report to flashrom@flashrom.org including a verbose
(-V) log.
Thank you!
Enabling flash write... Root Complex Register Block address = 0xfed1c000
GCS = 0x61: BIOS Interface Lock-Down: enabled, Boot BIOS Straps: 0x0 (SPI)
Top Swap: not enabled
0x7fffffff/0x7fffffff FWH IDSEL: 0x0
0x7fffffff/0x7fffffff FWH IDSEL: 0x0
0x7fffffff/0x7fffffff FWH IDSEL: 0x1
0x7fffffff/0x7fffffff FWH IDSEL: 0x1
0x7fffffff/0x7fffffff FWH IDSEL: 0x2
0x7fffffff/0x7fffffff FWH IDSEL: 0x2
0x7fffffff/0x7fffffff FWH IDSEL: 0x3
0x7fffffff/0x7fffffff FWH IDSEL: 0x3
0x7fffffff/0x7fffffff FWH IDSEL: 0x4
0x7fffffff/0x7fffffff FWH IDSEL: 0x5
0x7fffffff/0x7fffffff FWH IDSEL: 0x6
0x7fffffff/0x7fffffff FWH IDSEL: 0x7
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode disabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
0x7fffffff/0x7fffffff FWH decode enabled
Maximum FWH chip size: 0x100000 bytes
SPI Read Configuration: prefetching enabled, caching enabled,
BIOS_CNTL = 0x2a: BIOS Lock Enable: enabled, BIOS Write Enable: disabled
SPIBAR = 0x00007fc4b4d56000 + 0x3800
0x04: 0xe008 (HSFS)
HSFS: FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1
SPI Configuration is locked down.
Reading OPCODES... done
0x06: 0x0000 (HSFC)
HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0
0x50: 0x00004a4b (FRAP)
BMWAG 0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b
0x54: 0x00000000 FREG0: Flash Descriptor region (0x00000000-0x00000fff) is
read-only.
0x58: 0x07ff0400 FREG1: BIOS region (0x00400000-0x007fffff) is read-write.
0x5C: 0x03ff0001 FREG2: Management Engine region (0x00001000-0x003fffff) is
locked.
Not all flash regions are freely accessible by flashrom. This is most likely
due to an active ME. Please see https://flashrom.org/ME for details.
0x90: 0xc4 (SSFS)
SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0
0x91: 0xfc4540 (SSFC)
SSFC: SCGO=0, ACS=0, SPOP=0, COP=4, DBC=5, SME=0, SCF=4
0x94: 0x0006 (PREOP)
0x96: 0x043b (OPTYPE)
0x98: 0x05203b02 (OPMENU)
0x9c: 0x0000019f (OPMENU+4)
0xa0: 0x00000000 (BBAR)
0xc4: 0x80802025 (LVSCC)
LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1
0xc8: 0x00002025 (UVSCC)
UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20
0xd0: 0x50444653 (FPB)
Enabling hardware sequencing because some important opcode is locked.
OK.
The following protocols are supported: Programmer-specific.
Probing for Programmer Opaque flash chip, 0 kB: Hardware sequencing reports
1 attached SPI flash chip with a density of 8192 kB.
The first partition ranges from 0x000000 to 0x652fff.
In that range are 1619 erase blocks with 4096 B each.
The second partition ranges from 0x653000 to 0x7fffff.
In that range are 429 erase blocks with 4096 B each.
Found Programmer flash chip "Opaque flash chip" (8192 kB,
Programmer-specific) mapped at physical address 0x0000000000000000.
Found Programmer flash chip "Opaque flash chip" (8192 kB,
Programmer-specific).
No operations were specified.
Restoring MMIO space at 0x7fc4b4d598a0
Restoring PCI config space for 00:1f:0 reg 0xdc
[Attachment #5 (text/html)]
<div dir="ltr"><div class="gmail_default" style="font-family:times new \
roman,serif;font-size:large">flashrom v1.2 on Linux 5.15.58-2-lts \
(x86_64)<br>flashrom is free software, get the source code at <a \
href="https://flashrom.org">https://flashrom.org</a><br><br>flashrom was built with \
libpci 3.8.0, GCC 12.1.0, little endian<br>Command line (3 args): flashrom \
--programmer internal -V<br>Using clock_gettime for delay loops (clk_id: 1, \
resolution: 1ns).<br>Initializing internal programmer<br>get_mtd_info: device_name: \
"intel-spi", is_writeable: 0, numeraseregions: 0, total_size: 8388608, \
erasesize: 4096<br>No coreboot table found.<br>Using Internal DMI decoder.<br>No DMI \
table found.<br>Found chipset "Intel Lynx Point LP Premium" with PCI ID \
8086:9c43.<br>This chipset is marked as untested. If you are using an up-to-date \
version<br>of flashrom *and* were (not) able to successfully update your firmware \
with it,<br>then please email a report to <a \
href="mailto:flashrom@flashrom.org">flashrom@flashrom.org</a> including a verbose \
(-V) log.<br>Thank you!<br>Enabling flash write... Root Complex Register Block \
address = 0xfed1c000<br>GCS = 0x61: BIOS Interface Lock-Down: enabled, Boot BIOS \
Straps: 0x0 (SPI)<br>Top Swap: not enabled<br>0x7fffffff/0x7fffffff FWH IDSEL: \
0x0<br>0x7fffffff/0x7fffffff FWH IDSEL: 0x0<br>0x7fffffff/0x7fffffff FWH IDSEL: \
0x1<br>0x7fffffff/0x7fffffff FWH IDSEL: 0x1<br>0x7fffffff/0x7fffffff FWH IDSEL: \
0x2<br>0x7fffffff/0x7fffffff FWH IDSEL: 0x2<br>0x7fffffff/0x7fffffff FWH IDSEL: \
0x3<br>0x7fffffff/0x7fffffff FWH IDSEL: 0x3<br>0x7fffffff/0x7fffffff FWH IDSEL: \
0x4<br>0x7fffffff/0x7fffffff FWH IDSEL: 0x5<br>0x7fffffff/0x7fffffff FWH IDSEL: \
0x6<br>0x7fffffff/0x7fffffff FWH IDSEL: 0x7<br>0x7fffffff/0x7fffffff FWH decode \
enabled<br>0x7fffffff/0x7fffffff FWH decode enabled<br>0x7fffffff/0x7fffffff FWH \
decode enabled<br>0x7fffffff/0x7fffffff FWH decode enabled<br>0x7fffffff/0x7fffffff \
FWH decode enabled<br>0x7fffffff/0x7fffffff FWH decode \
enabled<br>0x7fffffff/0x7fffffff FWH decode enabled<br>0x7fffffff/0x7fffffff FWH \
decode enabled<br>0x7fffffff/0x7fffffff FWH decode disabled<br>0x7fffffff/0x7fffffff \
FWH decode enabled<br>0x7fffffff/0x7fffffff FWH decode \
enabled<br>0x7fffffff/0x7fffffff FWH decode enabled<br>Maximum FWH chip size: \
0x100000 bytes<br>SPI Read Configuration: prefetching enabled, caching enabled, \
<br>BIOS_CNTL = 0x2a: BIOS Lock Enable: enabled, BIOS Write Enable: \
disabled<br>SPIBAR = 0x00007fc4b4d56000 + 0x3800<br>0x04: 0xe008 (HSFS)<br>HSFS: \
FDONE=0, FCERR=0, AEL=0, BERASE=1, SCIP=0, FDOPSS=1, FDV=1, FLOCKDN=1<br>SPI \
Configuration is locked down.<br>Reading OPCODES... done<br>0x06: 0x0000 \
(HSFC)<br>HSFC: FGO=0, FCYCLE=0, FDBC=0, SME=0<br>0x50: 0x00004a4b (FRAP)<br>BMWAG \
0x00, BMRAG 0x00, BRWA 0x4a, BRRA 0x4b<br>0x54: 0x00000000 FREG0: Flash Descriptor \
region (0x00000000-0x00000fff) is read-only.<br>0x58: 0x07ff0400 FREG1: BIOS region \
(0x00400000-0x007fffff) is read-write.<br>0x5C: 0x03ff0001 FREG2: Management Engine \
region (0x00001000-0x003fffff) is locked.<br>Not all flash regions are freely \
accessible by flashrom. This is most likely<br>due to an active ME. Please see <a \
href="https://flashrom.org/ME">https://flashrom.org/ME</a> for details.<br>0x90: 0xc4 \
(SSFS)<br>SSFS: SCIP=0, FDONE=1, FCERR=0, AEL=0<br>0x91: 0xfc4540 (SSFC)<br>SSFC: \
SCGO=0, ACS=0, SPOP=0, COP=4, DBC=5, SME=0, SCF=4<br>0x94: 0x0006 \
(PREOP)<br>0x96: 0x043b (OPTYPE)<br>0x98: 0x05203b02 (OPMENU)<br>0x9c: \
0x0000019f (OPMENU+4)<br>0xa0: 0x00000000 (BBAR)<br>0xc4: 0x80802025 \
(LVSCC)<br>LVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20, VCL=1<br>0xc8: 0x00002025 \
(UVSCC)<br>UVSCC: BES=0x1, WG=1, WSR=0, WEWS=0, EO=0x20<br>0xd0: 0x50444653 \
(FPB)<br>Enabling hardware sequencing because some important opcode is \
locked.<br>OK.<br>The following protocols are supported: \
Programmer-specific.<br>Probing for Programmer Opaque flash chip, 0 kB: Hardware \
sequencing reports 1 attached SPI flash chip with a density of 8192 kB.<br>The first \
partition ranges from 0x000000 to 0x652fff.<br>In that range are 1619 erase blocks \
with 4096 B each.<br>The second partition ranges from 0x653000 to 0x7fffff.<br>In \
that range are 429 erase blocks with 4096 B each.<br>Found Programmer flash chip \
"Opaque flash chip" (8192 kB, Programmer-specific) mapped at physical \
address 0x0000000000000000.<br>Found Programmer flash chip "Opaque flash \
chip" (8192 kB, Programmer-specific).<br>No operations were \
specified.<br>Restoring MMIO space at 0x7fc4b4d598a0<br>Restoring PCI config space \
for 00:1f:0 reg 0xdc<br></div></div>
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